KSZ8993MLI Micrel Inc, KSZ8993MLI Datasheet - Page 53

2+1 Port 10/100 Switch W/Tranceivers & Frame Buffers, 128-Ld PQFP( , I-Temp)

KSZ8993MLI

Manufacturer Part Number
KSZ8993MLI
Description
2+1 Port 10/100 Switch W/Tranceivers & Frame Buffers, 128-Ld PQFP( , I-Temp)
Manufacturer
Micrel Inc
Datasheet

Specifications of KSZ8993MLI

Number Of Primary Switch Ports
3
Internal Memory Buffer Size
32
Fiber Support
Yes
Integrated Led Drivers
Yes
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
1.89/3.465V
Operating Supply Voltage (min)
1.71/3.135V
Power Dissipation
800mW
Operating Temperature Classification
Industrial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Supplier Unconfirmed
Other names
576-3350

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KSZ8993MLI
Manufacturer:
Micrel Inc
Quantity:
10 000
Part Number:
KSZ8993MLI
Manufacturer:
MICREL/麦瑞
Quantity:
20 000
Register 6 (0x06): Global Control 4 (continued)
Bit
3
2-0
Register 7 (0x07): Global Control 5
Bit
7-0
Note: Rate: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.) = 0x63
Register 8 (0x08): Global Control 6
Bit
7-0
Register 9 (0x09): Global Control 7
Bit
7-0
Register 10 (0x0A): Global Control 8
Bit
7-0
Register 11 (0x0B): Global Control 9
Bit
7
6
5
4
3
Micrel, Inc.
October 2008
Null VID
replacement
Broadcast
storm
protection rate
Bit [10:8]
Broadcast
storm
protection
rate
Bit [7:0]
PHY
power
save
Name
Name
Name
Factory testing
Name
Factory testing
Name
Factory testing
Name
Reserved
Reserved
Reserved
Reserved
(1)
R/W
R/W
R/W
RW
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
= 1, enable PHY power save mode
= 0, disable PHY power save mode
Reserved
Testing mode, must be 0
Reserved
Description
= 1, will replace NULL VID with port VID(12 bits)
= 0, no replacement for NULL VID
This register along with the next register determines
how many “64 byte blocks” of packet data allowed on
an input port in a preset period. The period is 50ms
for 100BT or 500ms for 10BT. The default is 1%.
Description
This register along with the previous register
determines how many “64 byte blocks” of packet data
are allowed on an input port in a preset period. The
period is 67ms for 100BT or 500ms for 10BT. The
default is 1%.
Description
Reserved
Description
Reserved
Description
Reserved
53
Default
0
000
Default
0x63
Default
0x4E
Default
0x24
Default
0x24
Default
0
0
0
0
1
M9999-020606
KSZ8993M/ML

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