SCAN90CP02VY National Semiconductor, SCAN90CP02VY Datasheet - Page 2

• Manufacturer Part Number: SCAN90CP02VY
• Manufacturer: National Semiconductor

Specifications of SCAN90CP02VY

• Array Configuration: 2x2
• Number Of Arrays: 1
• Differential Data Transmission: Yes
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Cascading Capability: No
• On-chip Buffers: No
• On-chip Decoder: No
• On-chip Latch Circuit: No
• On-chip Mux/demux: No
• Programmable: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Output Level: LVDS
• Lead Free Status / RoHS Status: Not Compliant

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DIFFERENTIAL INPUTS COMMON TO ALL MUXES
IN0+
IN0−
IN1+
IN1−
SWITCHED DIFFERENTIAL OUTPUTS
OUT0+
OUT0−
OUT1+
OUT1−
DIGITAL CONTROL INTERFACE
SEL0,
SEL1
EN0, EN1
PEM00,
PEM01
PEM10,
PEM11
TDI
TDO
TMS
TCK
TRST
N/C
POWER
V
GND
DD
Pin Descriptions
Name
Note 1: Note that for the LLP package GND is not an actual pin on the package, the GND is connected thru the DAP on the back side of the LLP package.
Note 2: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN90CP02 device have been optimized
for point-to-point backplane and cable applications.
Pin
16, 22, 25
Number
LLP Pin
(Note 1) 5, 11, 15,
11, 14,
8, 28
10
12
13
27
26
24
23
15
19
20
18
17
21
9
6
5
7
4
3
2
1
18, 25, 29
20, 26, 30
Number
12, 16,
LQFP
Pin
10
13
14
32
31
28
27
17
22
23
21
19
24
9
7
6
8
4
3
2
1
O, LVTTL
I/O, Type
O, LVDS
O, LVDS
I, LVTTL
I, LVTTL
I, LVTTL
I, LVTTL
I, LVTTL
I, LVTTL
I, LVTTL
I, LVTTL
I, Power
I, LVDS
I, LVDS
Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL
compatible.
Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL
compatible.
Inverting and non-inverting differential outputs. OUT0± can be connected to any
one pair IN0±, or IN1±. LVDS compatible (Note 2).
Inverting and non-inverting differential outputs. OUT1± can be connected to any
one pair IN0±, or IN1±. LVDS compatible (Note 2).
Select Control Inputs
Output Enable Inputs
Channel 0 Output Pre-emphasis Control Inputs
Channel 1 Output Pre-emphasis Control Inputs
Test Data Input to support IEEE 1149.1 features
Test Data Output to support IEEE 1149.1 features
Test Mode Select to support IEEE 1149.1 features
Test Clock to support IEEE 1149.1 features
Test Reset to support IEEE 1149.1 features
Not Connected
V
connected from V
Ground reference to LVDS and CMOS circuitry.
For the LLP package, the DAP is used as the primary GND connection to the
device. The DAP is the exposed metal contact at the bottom of the LLP-28
package. It should be connected to the ground plane with at least 4 vias for optimal
AC and thermal performance.
DD
= 3.3V ±0.3V. At least 4 low ESR 0.01 µF bypass capacitors should be
2
DD
to GND plane.
Description