5962-8953202QA QP SEMICONDUCTOR, 5962-8953202QA Datasheet - Page 10

• Manufacturer Part Number: 5962-8953202QA
• Manufacturer: QP SEMICONDUCTOR

Specifications of 5962-8953202QA

• Lead Free Status / RoHS Status: Not Compliant

DSCC FORM 2234
APR 97
1/
2/
3/
4/
5/
6/
7/
8/
9/
10/ This specification is made only to insure that DTACKN is asserted with respect to the rising edge of the X1/CLK pin as
TxC high or low time
TxC frequency (16X)
TxC frequency (1X)
TxD output delay from TxC
Output delay from TxC low
RxD data setup time to
RxD data hold time from
low
to TxD data output
RxC high
RxC high
All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V
and 2.4 V with a transition time of < 20 ns. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements
referenced at input voltages of 0.8 V and 2.0 V as appropriate.
Test condition for outputs: C
Test condition for interrupt outputs: C
For CMOS technology: I
Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the
“strobing” input. In this case, all timing specifications apply referenced to the falling and rising edges of CEN. CEN and
RDN (also CEN and WRN) are AND’ed internally. As a consequence, the signal asserted last initiates the cycle and the
signal negated first terminates the cycle.
If CEN is used as the “strobing” input, the parameter defines the minimum high times between one CEN and the next. The
RDN signal must be negated for t
Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
Minimum frequencies may not be tested, but are guaranteed by design.
This specification will impose maximum 68000 CPU CLK to 6 MHz. Higher CPU CLK can be used if repeating bus reads
are not performed. Consecutive write operations to the same command register require at least three edges of the X1
clock between writes.
This specification imposed a lower bound on CSN and IACKN low, guaranteeing that it will be low for at least 1 CLK period.
shown in the timing diagram, not to guarantee operation of the part. If the setup time is violated, DTACKN may be
asserted as shown, or may be asserted one clock cycle later.
This requirement is made on CSN only to insure assertion of DTACKN and not to guarantee operation of the part.
DEFENSE SUPPLY CENTER COLUMBUS
Test
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43218-3990
STANDARD
IL(X2)
t
f
f
t
t
t
t
Symbol
TX
TX
TX
TXD
TCS
RXS
RXH
TABLE I. Electrical performance characteristics - Continued.
L
X1/CLK = V
= 150 pF tied to ground, except interrupt outputs.
RWD
to guarantee that any status register changes are valid.
L
See figure 4.
unless otherwise specified
= 50 pF tied to ground, R
4.5 V dc ≤ V
CC
-55°C ≤ T
, I
Conditions
IH(X2)
X1/CLK = 0.0 V.
C
CC
4/
≤ +125°C
≤ 5.5 V dc
1/ 2/
L
SIZE
= 2.7 kΩ to V
A
subgroups
9, 10, 11
Group A
REVISION LEVEL
CC
.
Device
type
03
C
Min
220
240
200
0
0
0
Limits
SHEET
Max
350
150
2.0
1.0
5962-89532
10
MHz
MHz
Unit
ns
ns
ns
ns
ns