PXB4221EV34NP Lantiq, PXB4221EV34NP Datasheet - Page 93

• Manufacturer Part Number: PXB4221EV34NP
• Manufacturer: Lantiq

Specifications of PXB4221EV34NP

• Data Rate: 2.048Mbps
• Number Of Channels: 1
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

FTFRS[7:0]
RFCLK
The receive system clock and transmit system clock are both 8.192 MHz, and may be
independent from each other. The data rate is 2048 Mbit/s. This means that each bit lasts
for 4 clock cycles.
Data on the system internal highway is structured in frames of 256 bits every 125 s . It
is transmitted in 32 slots numbered from 0 to 31 with slot 0 transmitted first. The data bits
of a slot are numbered from 1 to 8. The first transmitted bit ‘bit 1’ is the most significant
bit.
Data Sheet
Figure 23
shows the bit ordering.
0 =
1 =
Framer Transmit Frame Synchronization Pulse
FTFRS is generated at the beginning of timslot 1 of every frame
Reference Clock
• Reference clock for the internal clock recovery circuit
• Depending on p_rx_em in pcfN: Optional emergency clock if
no transition on FRCLK is detected within 23 CLOCK cycles.
The segmentation continues using the RFCLK divided by four,
and using the byte-pattern programmed to a_emg_bpslct in
acfg for the cell payload.
Structured CES: Depending on “p_tx_mfs” in
“pcfN”:
0 = Double frame mode: FTMFS is asserted every
2 frames (250 µs)
1 =
E1 CRC multiframe mode: FTMFS is asserted
every 16 frames (2 ms)
T1 mode: every 3 ms
T1 superframe mode: every 1.5 ms
Unstructured CES: Unused, constant low level
93
PXB 4219E, PXB 4220E, PXB 4221E
Interface Description
IWE8, V3.4
2003-01-20