LT1739IUE#PBF Linear Technology, LT1739IUE#PBF Datasheet - Page 12

• Manufacturer Part Number: LT1739IUE#PBF
• Manufacturer: Linear Technology

Specifications of LT1739IUE#PBF

• Power Supply Requirement: Dual
• Slew Rate: 200V/us
• Pin Count: 12
• Lead Free Status / RoHS Status: Compliant

APPLICATIO S I FOR ATIO
Layout and Passive Components
With a gain bandwidth product of 200MHz the LT1739
requires attention to detail in order to extract maximum
performance. Use a ground plane, short lead lengths and
a combination of RF-quality supply bypass capacitors (i.e.,
0.1 F). As the primary applications have high drive cur-
rent, use low ESR supply bypass capacitors (1 F to 10 F).
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with the
input capacitance to form a pole that can cause frequency
peaking. In general, use feedback resistors of 1k or less.
Compensation
The LT1739 is stable in a gain 10 or higher for any supply
and resistive load. It is easily compensated for lower gains
with a single resistor or a resistor plus a capacitor.
Figure 9 shows that for inverting gains, a resistor from the
inverting node to AC ground guarantees stability if the
LT1739
12
(OPTIONAL)
C
V
C
R
I
V
G
i
Figure 11. Alternate Noninverting Compensation
R
Figure 9. Compensation for Inverting Gains
C
G
C
R
+
–
C
R
F
U
–
+
R
U
F
V
O
2 R
R
V
V
G
O
I
1
G
= 1 (LOW FREQUENCIES)
= 1 +
R
C
C
F
/9
W
< 5MHz
R
V
R
O
G
F
(HIGH FREQUENCIES)
2 R
V
(R
V
O
I
C
1
=
C
|| R
C
–R
R
C
U
G
G
< 5MHz
F
) R
1739 F11
1739 F09
F
/9
parallel combination of R
R
capacitor, C
lower frequencies. The break frequency produced by R
and C
Figure 10 shows compensation in the noninverting con-
figuration. The R
ing case. The input impedance is not reduced because the
network is bootstrapped. This network can also be placed
between the inverting input and an AC ground.
Another compensation scheme for noninverting circuits is
shown in Figure 11. The circuit is unity gain at low
frequency and a gain of 1 + R
DC output offset is reduced by a factor of ten. The
techniques of Figures 10 and 11 can be combined as
shown in Figure 12. The gain is unity at low frequencies,
1 + R
greater at high frequencies.
C
V
F
BIG
C
I
/9. For lowest distortion and DC output offset, a series
R
C
R
C
G
(OPTIONAL)
F
C
/R
Figure 10. Compensation for Noninverting Gains
should be less than 5MHz to minimize peaking.
G
V
C
I
at mid-band and for stability, a gain of 10 or
C
R
R
Figure 12. Combination Compensation
G
C
C
+
–
, can be used to reduce the noise gain at
C
R
, C
F
C
+
–
network acts similarly to the invert-
C
R
F
and R
V
V
V
O
F
O
I
/R
= 1 AT LOW FREQUENCIES
= 1 +
= 1 +
G
G
is less than or equal to
at high frequency. The
R
(R
R
G
F
C
V
AT MEDIUM FREQUENCIES
R
O
|| R
F
G
)
2 R
V
(R
AT HIGH FREQUENCIES
V
O
I
C
1
C
= 1 +
|| R
C
C
G
< 5MHz
1739fas, sn1739
) R
R
R
1739 F10
G
F
F
/9
1739 F12
C