IMIZ9972BA Cypress Semiconductor Corp, IMIZ9972BA Datasheet - Page 2

• Manufacturer Part Number: IMIZ9972BA
• Manufacturer: Cypress Semiconductor Corp

Specifications of IMIZ9972BA

• Number Of Outputs: 12
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Propagation Delay Time: 0.53ns
• Operating Supply Voltage (min): 2.97V
• Mounting: Surface Mount
• Pin Count: 52
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Duty Cycle: 75%
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-07088 Rev. *D
Pin Descriptions
Note:
44, 46, 48, 50
32, 34, 36, 38
16, 18, 21, 23
35, 39, 47, 51
33,37, 45, 49
1, 15, 24, 30,
2.
17, 22, 28,
5, 26, 27
A bypass capacitor (0.1 F) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
42, 43
40, 41
19, 20
Pin
12
10
29
25
52
31
14
13
11
9
6
7
8
2
3
4
FB_SEL(2:0)
TCLK_SEL
SELA(1,0)
SELB(1,0)
SELC(1,0)
VCO_SEL
REF_SEL
INV_CLK
FB_OUT
MR#/OE
PLL_EN
VDDC
QA(3:0)
QB(3:0)
QC(3:0)
TCLK0
TCLK1
SDATA
VDD
XOUT
SYNC
FB_IN
Name
SCLK
VSS
XIN
[2]
[2]
VDDC
VDDC
VDDC
VDDC
VDDC
PWR
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
Oscillator Input. Connect to a crystal.
Oscillator Output. Connect to a crystal.
External Reference/Test Clock Input.
External Reference/Test Clock Input.
Clock Outputs. See Table 2 for frequency selections.
Clock Outputs. See Table 2 for frequency selections.
Clock Outputs. See Table 2 for frequency selections.
Feedback Clock Output. Connect to FB_IN for normal operation. The
divider ratio for this output is set by FB_SEL(0:2). See Table 1. A bypass
delay capacitor at this output will control Input Reference/ Output Banks
phase relationships.
Synchronous Pulse Output. This output is used for system synchroni-
zation. The rising edge of the output pulse is in sync with both the rising
edges of QA (0:3) and QC(0:3) output clocks regardless of the divider
ratios selected.
Frequency Select Inputs. These inputs select the divider ratio at QA(0:3)
outputs. See Table 2.
Frequency Select Inputs. These inputs select the divider ratio at QB(0:3)
outputs. See Table 2.
Frequency Select Inputs. These inputs select the divider ratio at QC(0:3)
outputs. See Table 2.
Feedback Select Inputs. These inputs select the divide ratio at FB_OUT
output. See Table 2.
VCO Divider Select Input. When set LOW, the VCO output is divided by
2. When set HIGH, the divider is bypassed. See Table 1.
Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
PLL Enable Input. When asserted HIGH, PLL is enabled. And when
LOW, the phase-lock loop (PLL) is bypassed.
Reference Select Input. When HIGH, the crystal oscillator is selected.
And when LOW, TCLK (0,1) is the reference clock.
TCLK Select Input. When LOW, TCLK0 is selected and when HIGH
TCLK1 is selected.
Master Reset/Output Enable Input. When asserted LOW, resets all of
the internal flip-flops and also disables all of the outputs. When pulled
HIGH, releases the internal flip-flops from reset and enables all of the
outputs.
Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted.
When set LOW, the inverter is bypassed.
Serial Clock Input. Clocks data at SDATA into the internal register.
Serial Data Input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
3.3V Power Supply for Output Clock Buffers.
3.3V Supply for PLL.
Common Ground.
Description
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Z9972
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