PI90LVT14LEX Pericom Semiconductor, PI90LVT14LEX Datasheet - Page 3

• Manufacturer Part Number: PI90LVT14LEX
• Description: Clock Drivers & Distribution 1:5 LVDS Clock Distribution
• Manufacturer: Pericom Semiconductor
• Type: Clock Driverr

Specifications of PI90LVT14LEX

• Number Of Clock Inputs: 2
• Output Logic Level: LVDS
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVDS/LVTTL/TTL
• Mounting: Surface Mount
• Pin Count: 20
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Multiply / Divide Factor: 2:1
• Number Of Outputs: /
• Maximum Operating Temperature: + 85 C
• Package / Case: TSSOP-20
• Lead Free Status / RoHS Status: Compliant

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Switching Characteristics over Recommended Operating Conditions
Notes:
1. Within-Device skew is defined for identical transitions on similar paths through a device.
2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK.
3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated with only 50mV
4. The range in which the high level of the input swing must fall while meeting the V
5. t
6. t
7. Generator input conditions: t
8. C
9. Generator waveform for all tests unless otherwise specified: f = 25 MHz, Z
C
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C
C
P
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P
H
M
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D
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S
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C
C
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y
E
E
o
S
S
a h
o
u
input swings.
any given temperature and V
temperature.
direction. This parameter is guaranteed by design and characterization.
Output Criteria: 60%/40% duty cycle, V
propagation delay & minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V.
N
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SKIR
SK2R
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N
N
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is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same
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CC
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< 1ns, 50% duty cycle, differential (1.10V to 1.35V peak-peak).
. The propagation delay specification is a device-to-device worst case over process, voltage, and
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e
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t (
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P
L
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OL
t -
(max) 0-4V, V
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R
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(min) 2.7V, Load - 7pF (stray plus probes).
PHL
) of one device, and is the duty cycle distortion of the output at
3
0
M
. 0
–
–
1
1
1
1
1 .
0 5
2 2
0 0
0 0
0 5
0 5
0 2
. n i
5 2
O
= 50 ohms, t
1 –
1 –
T
5
5
2
2
4
3
2
2
2
2
3
1
0 7
y
0 5
0 0
0 0
0 5
0 .
5 .
6 .
7 .
7 .
7 .
7 .
5 .
0 0
0 0
. p
PP
(unless otherwise noted)
spec.
r
= 1ns, t
V
C
M
0
C
T
T
T
2 1
2 1
+
+
7
7
3
1
4
3
3
3
3
6
6
8 .
B
B
B
0 5
2 2
0 2
0 2
0 0
-
0 9
f
a
0 .
5 .
6 .
5 .
5 .
0 .
0 .
0 0
0 0
0 0
D
D
D
= 1ns (35%-65%). To ensure fastest
. x
. 0
0 2
PI90LV14/PI90LVT14
1:5 Clock Distribution
U
M
n
s n
s n
s p
s p
V
H
(8,9)
s t i
z
.
PS8538D
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i F
o
n
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d
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2
2
3
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6
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t i
o i
6
7
10/27/09
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