MC100ES6535DT Freescale, MC100ES6535DT Datasheet - Page 2

• Manufacturer Part Number: MC100ES6535DT
• Manufacturer: Freescale

Specifications of MC100ES6535DT

• Lead Free Status / RoHS Status: Not Compliant

MPC100ES6535 Data Sheet
Table 1. Pin Description
Table 2. Control Input Function Table
MPC100ES6535 REVISION 4 JUNE 9, 2009
1. Pullup and Pulldown refer to internal input resistors.
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge. In the active mode, the
10, 13, 18
5, 7, 8, 9
Number
state of the outputs are a function of the CLK0 and CLK1 inputs as described in .
11, 12
14, 15
16, 17
19, 20
1
2
3
4
6
CLK_EN
0
0
1
1
CLK_EN
CLK0
CLK1
CLK_SEL
CLK_SEL
CLK_EN
Q3, Q3
Q2, Q2
Q1, Q1
Q0, Q0
Name
CLK0
CLK1
V
V
NC
CC
EE
0
1
CLK_SEL
Figure 1. Logic Diagram
Unused
Output
Output
Output
Output
Power
Power
Inputs
Input
Input
Input
Input
0
1
0
1
(1)
Type
D
LE
Pulldown
Pulldown
Pulldown
Q
Pullup
(1)
Selected Source
(1)
(1)
(1)
Negative supply pin
Positive supply pin
Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q
outputs are forced low, Q outputs are forced high. LVCMOS/LVTTL interface levels
Clock select input. When HIGH, selects CLK1 input.. When LOW, selects CLK0 input.
LVCMOS/LVTTL interface levels
LVCMOS/LVTTL clock input
LVCMOS/LVTTL clock input
No connect
LVPECL differential output pair
LVPECL differential output pair
LVPECL differential output pair
LVPECL differential output pair
CLK0
CLK1
CLK0
CLK1
2
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Disabled; LOW
Disabled; LOW
Enabled
Enabled
CLK_SEL
Q0:Q3
CLK_EN
CLK0
CLK1
V
V
NC
NC
NC
CC
EE
nc
Figure 2. 20-Lead Pinout (Top View)
Description
Outputs
3.3V LVCMOS-TO-LVPECL 1:4 FANOUT BUFFER
1
2
3
4
5
6
7
8
9
10
MC100ES6535
©2009 Integrated Device Technology, Inc.
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
Q0:Q3
20
19
18
17
16
15
14
13
12
11
Q0
Q0
V
Q1
Q1
Q2
Q2
V
Q3
Q3
CC
CC