CY29949AC Cypress Semiconductor Corp, CY29949AC Datasheet

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CY29949AC

Manufacturer Part Number
CY29949AC
Description
Manufacturer
Cypress Semiconductor Corp
Type
Clock Dividerr
Datasheet

Specifications of CY29949AC

Number Of Clock Inputs
3
Output Frequency
200MHz
Output Logic Level
LVCMOS/LVTTL
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.63V
Package Type
TQFP
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Signal Type
LVCMOS/LVPECL/LVTTL
Mounting
Surface Mount
Pin Count
52
Quiescent Current
7mA
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY29949AC
Manufacturer:
CY
Quantity:
889
Cypress Semiconductor Corporation
Document #: 38-07289 Rev. *E
Features
Logic Block Diagram
2.5V or 3.3V operation
200-MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS/LVTTL compatible outputs
15 clock outputs: drive up to 30 clock lines
1X and 1/2X configurable outputs
Output three-state control
350 ps maximum output-to-output skew
Pin compatible with MPC949, MPC9449
Available in Commercial and Industrial temperature range
52-pin TQFP package
PECL_CLK#
PECL_SEL
PECL_CLK
TCLK_SEL
MR/OE#
DSELC
DSELD
DSELA
DSELB
198 Champion Court
0
1
1
0
R
R
R
R
1
2
2
2
2
1
1
1
Description
The CY29949 is a low voltage 200 MHz clock distribution
buffer with the capability to select either a differential LVPECL
or LVCMOS/LVTTL compatible input clocks. These clock
sources are used to provide for test clocks and primary system
clocks. All other control inputs are LVCMOS/LVTTL
compatible. The 15 outputs are LVCMOS or LVTTL compatible
and can drive 50Ω series or parallel terminated transmission
lines. For series terminated transmission lines, each output
can drive one or two traces giving the device an effective
fanout of 1:30.
The CY29949 is capable of generating 1X and 1/2X signals
from a 1X source. These signals are generated and retimed
internally to ensure minimal skew between the 1X and 1/2X
signals. SEL(A:D) inputs allow flexibility in selecting the ratio
of 1X to1/2X outputs.
The CY29949 outputs can also be three-stated via the
MR/OE# input. When MR/OE# is set HIGH, it resets the
internal flip-flops and three-states the outputs.
0
1
0
1
0
1
0
1
2.5V or 3.3V 200 MHz 1:15
San Jose
Clock Distribution Buffer
6
3
4
2
,
QA(0:1)
QB(0:2)
QC(0:3)
QD(0:5)
CA 95134-1709
Revised October 22, 2008
CY29949
408-943-2600
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CY29949AC Summary of contents

Page 1

... TQFP package ■ Logic Block Diagram TCLK_SEL PECL_CLK PECL_CLK# PECL_SEL Cypress Semiconductor Corporation Document #: 38-07289 Rev. *E 2.5V or 3.3V 200 MHz 1:15 Clock Distribution Buffer Description The CY29949 is a low voltage 200 MHz clock distribution buffer with the capability to select either a differential LVPECL or LVCMOS/LVTTL compatible input clocks ...

Page 2

Pin Configuration MR/OE# TCLK_SEL PECL_CLK PECL_CLK# PCLK_SEL Pin Description Pin Name 6 PECL_CLK 7 PECL_CLK TCLK(0,1) 49, 51 QA(1,0) VDDC 42, 44, 46 QB(2:0) VDDC 31, 33, 35, 37 QC(3:0) VDDC 16, 18, 20, 22, 24, 28 QD(5:0) ...

Page 3

Maximum Ratings [2] Maximum Input Voltage Relative to V :............. V SS Maximum Input Voltage Relative to V :............. V DD Storage Temperature: ................................ –65° 150°C Operating Temperature:................................ –40°C to +85°C Maximum ESD Protection .............................................. 2 kV Maximum ...

Page 4

AC Parameters ( 3.3V ±10% or 2.5V ±5%, over the specified temperature range) DD DDC Parameter Description [7] Fmax Input Frequency [7] Tpd PECL_CLK to Q Delay [7] TCLK to Q Delay [7] PECL_CLK to Q Delay ...

Page 5

Figure 4. Propagation Delay (TPD) Test Reference PECL_CLK PECL_CLK Figure 5. LVCMOS Propagation Delay (TPD) Test Reference LVCMOS_CLK Document #: 38-07289 Rev Figure 6. Output Duty Cycle (FoutDC ...

Page 6

Ordering Information Part Number CY29949AXI 52-Pin TQFP CY29949AXIT 52-Pin TQFP - Tape and Reel CY29949AXC 52-Pin TQFP CY29949AXCT 52-Pin TQFP - Tape and Reel Package Drawing and Dimensions Figure 8. 52-Pin Thin Plastic Quad Flat Pack ( ...

Page 7

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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