ZZZZMC100LVEP14DT ON Semiconductor, ZZZZMC100LVEP14DT Datasheet - Page 5
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ZZZZMC100LVEP14DT
Manufacturer Part Number
ZZZZMC100LVEP14DT
Description
Manufacturer
ON Semiconductor
Type
Clock Driverr
Datasheet
1.ZZZZMC100LVEP14DT.pdf
(7 pages)
Specifications of ZZZZMC100LVEP14DT
Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Logic Level
ECL/PECL
Operating Supply Voltage (min)
-2.375/2.375V
Operating Supply Voltage (typ)
-2.5/-3.3/2.5/3.3V
Operating Supply Voltage (max)
-3.8/3.8V
Package Type
TSSOP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Signal Type
ECL/HSTL/PECL
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Compliant
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V
15. Skew is measured between outputs under identical transitions.
Table 8. DC CHARACTERISTICS, HSTL
Table 9. AC CHARACTERISTICS
t
V
V
V
t
t
t
t
t
V
t
Symbol
Symbol
JITTER
PLH
PHL
skew
s
h
r
/t
IH
IL
OUTPP
PP
f
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Input HIGH Voltage
Input LOW Voltage
Output Voltage Amplitude @ 2.5 GHz
(Figure 2)
Propagation Delay to
Output Differential
Within−Device Skew (Note 15)
Device−to−Device Skew (Note 15)
Setup Time
Hold Time
CLOCK Random Jitter (RMS)
@ v 1.0 GHz
@ v 1.5 GHz
@ v 2.0 GHz
@ v 2.5 GHz
Minimum Input Swing
Output Rise/Fall Time (20%−80%)
Characteristic
Characteristic
V
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
CC
= 0 V, V
EN
EN
V
CC
1200
Min
EE
= 2.375 V to 3.8 V, V
Min
330
300
100
200
150
125
= −2.375 V to −3.8 V or V
− ECL Clock Distribution Techniques
− Designing with PECL (ECL at +5.0 V)
− ECLinPSt I/O SPiCE Modeling Kit
− Metastability and the ECLinPS Family
− Interfacing Between LVDS and ECL
− The ECL Translator Guide
http://onsemi.com
−40°C
Typ
−40°C
0.157
0.163
0.180
0.179
Typ
425
375
100
140
800
165
10
50
5
Max
400
1200
Max
425
125
225
0.3
0.2
0.3
0.3
25
EE
= 0 V
1200
Min
Min
280
300
100
200
150
125
CC
= 2.375 V to 3.8 V; V
25°C
0.181
0.176
0.201
0.208
Typ
25°C
Typ
375
400
150
140
800
180
15
50
CC
− 2.0 V.
Max
1200
400
Max
475
175
250
0.3
0.3
0.3
0.3
25
EE
1200
Min
Min
230
300
100
200
150
125
= 0 V (Note 14)
0.212
0.218
0.235
0.253
85°C
85°C
Typ
Typ
295
430
200
140
800
200
15
50
1200
Max
Max
400
525
225
275
0.3
0.3
0.3
0.4
25
Unit
Unit
mV
mV
mV
mV
ps
ps
ps
ps
ps