MC10H644FN ON Semiconductor, MC10H644FN Datasheet

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MC10H644FN

Manufacturer Part Number
MC10H644FN
Description
Manufacturer
ON Semiconductor
Datasheet

Specifications of MC10H644FN

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MC10H644, MC100H644
68030/040 PECL to TTL
Clock Driver
68030, 68040 and similar microprocessors. The device is functionally
equivalent to the H640, but with fewer outputs in a smaller outline
20−lead PLCC package. It is guaranteed to meet the clock
specifications required by the 68030 and 68040 in terms of
part−to−part skew, within−part skew and also duty cycle skew.
to +5.0 V) for the input clock. TTL clocks are typically used in present
MPU systems. However, as clock speeds increase to 50 MHz and
beyond, the inherent superiority of ECL (particularly differential
ECL) as a means of clock signal distribution becomes increasingly
evident. The H644 also uses differential ECL internally to achieve its
superior skew characteristic.
to achieve the necessary duty cycle and skew to generate MPU clocks
as required. A typical 50 MHz processor application would use an
input clock running at 100 MHz, thus obtaining output clocks at
50 MHz and 25 MHz (see Logic Symbol).
while the 100H version is compatible with 100K levels (referenced
to +5.0 V).
Function
outputs HIGH.
edges of the ÷2 and ÷4 outputs synchronized.
selects the TTL input source (DT).
input differential pair, should both sides be left open. In this case, the
DE side of the input is pulled LOW, and DE goes HIGH.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
The MC10H/100H644 generates the necessary clocks for the
The user has a choice of using either TTL or PECL (ECL referenced
The H644 includes divide−by−two and divide−by−four stages, both
The 10H version is compatible with MECL™ 10H ECL logic levels,
Reset (R): LOW on RESET forces all Q outputs LOW and all Q
Synchronized Outputs: The device is designed to have the POS
Select (SEL): LOW selects the PECL input source (DE/DE). HIGH
The H644 also contains circuitry to force a stable state of the PECL
Generates Clocks for 68030/040
Meets 68030/040 Skew Requirements
TTL or PECL Input Clock
Extra TTL and ECL Power/Ground Pins
Within Device Skew on Similar Paths is 0.5 ns
Asynchronous Reset
Single +5.0 V Supply
1
MC10H644FN
MC100H644FN
Device
FN SUFFIX
CASE 775
PLCC−20
ORDERING INFORMATION
A
WL
YY
WW
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
PLCC−20
PLCC−20
Package
Publication Order Number:
MARKING
DIAGRAM
AWLYYWW
10H644
37 Units/Rail
37 Units/Rail
Shipping
MC10H644/D
1

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MC10H644FN Summary of contents

Page 1

... Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 6 http://onsemi.com PLCC−20 FN SUFFIX CASE 775 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week ORDERING INFORMATION Device Package MC10H644FN PLCC−20 MC100H644FN PLCC−20 1 MARKING DIAGRAM 1 10H644 AWLYYWW Shipping 37 Units/Rail 37 Units/Rail Publication Order Number: MC10H644/D ...

Page 2

SEL DT Figure 1. Pinout: PLCC−20 (Top ...

Page 3

Table 2. 10H PECL DC CHARACTERISTICS Symbol Characteristic I Input HIGH Current INH I Input LOW Current INL V * Input HIGH Voltage Input LOW Voltage Output Reference Voltage BB NOTE: Device will meet ...

Page 4

Table 6. AC CHARACTERISTICS (V Symbol Characteristic t Propagation Delay ECL PLH D to Output t Propagation Delay TTL PLH D to Output t * Within−Device Skew skwd t * Within−Device Skew skwd t * Within−Device Skew skwd t * ...

Page 5

Y BRK −N− −L− −M− 0.007 (0.180) Z 0.007 (0.180 −T− J VIEW S G1 0.010 (0.250) T L− NOTES: 1. DATUMS −L−, −M−, AND −N− DETERMINED ...

Page 6

... Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 6 ON Semiconductor Website: http://onsemi ...

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