LFE2M35E-6FN256I LATTICE SEMICONDUCTOR, LFE2M35E-6FN256I Datasheet - Page 20
LFE2M35E-6FN256I
Manufacturer Part Number
LFE2M35E-6FN256I
Description
FPGA LatticeECP2M Family 34000 Cells 90nm (CMOS) Technology 1.2V 256-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M35E-6FN256I
Package
256FBGA
Family Name
LatticeECP2M
Device Logic Units
34000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
140
Ram Bits
2151424
In System Programmability
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M35E-6FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 2-16. Secondary Clock Selection
Slice Clock Selection
Figure 2-17 shows the clock selections and Figure 2-18 shows the control selections for Slice0 through Slice2. All
the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals can be used
as a clock input to the slices via routing. Slice controls are generated from the secondary clocks or other signals
connected via routing.
If none of the signals are selected for both clock and control then the default value of the mux output is 1. Slice 3
does not have any registers; therefore it does not have the clock or control muxes.
Figure 2-17. Slice0 through Slice2 Clock Selection
4 Secondary Clocks/CE/LSR (SC0 to SC3) per Region
SC0
24:1
Secondary Clock
Primary Clock
SC1
24:1
Clock/Control
Routing
Secondary Clock Feedlines: 8 PIOs + 16 Routing
SC2
Vcc
24:1
SC3
12
24:1
8
4
1
4 High Fan-out Data Signals (SC4 to SC7) per Region
2-17
SC4
24:1
25:1
SC5
High Fan-out Data
24:1
LatticeECP2/M Family Data Sheet
Clock to Slice
SC6
24:1
SC7
24:1
Architecture
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