XC5VLX50T-1FFG665I Xilinx Inc, XC5VLX50T-1FFG665I Datasheet - Page 121

• Manufacturer Part Number: XC5VLX50T-1FFG665I
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665I

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Simple Dual-Port Block RAM
Each 18 Kb block and 36 Kb block can also be configured in a simple dual-port RAM mode.
In this mode, the block RAM port width doubles to 36 bits for the 18 Kb block RAM and
72 bits for the 36 Kb block RAM. In simple dual-port mode, independent Read and Write
operations can occur simultaneously, where port A is designated as the Read port and port
B as the Write port. When the Read and Write port access the same data location at the
same time, it is treated as a collision, similar to the port collision in true dual-port mode.
Readback through the configuration port is not supported in simple dual-port block RAM
mode.
X-Ref Target - Figure 4-6
Table 4-3: Simple Dual-Port Names and Descriptions
Port Names
WRADDR
RDADDR
WRCLK
RDCLK
REGCE
WREN
RDEN
DOP
Figure 4-6
DIP
SSR
WE
DO
DI
shows the simple dual-port data flow.
Data Output Bus
Data Output Parity Bus
Data Input Bus
Data Input Parity Bus
Read Data Address Bus
Read Data Clock
Read Port Enable
Output Register Clock Enable
Synchronous Set/Reset
Byte-wide Write Enable
Write Data Address Bus
Write Data Clock
Write Port Enable
Figure 4-6: Simple Dual-Port Data Flow
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8
8
9
9
DIP
WE
WEADDR
WRCLK
WREN
DI
RDEN
RDADDR
RDCLK
REGCE
SSR
36 Kb Memory Array
Additional Block RAM Features in Virtex-5 Devices
Descriptions
DOP
DO
ug190_4_02_041206
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