LFXP3C-3TN100C LATTICE SEMICONDUCTOR, LFXP3C-3TN100C Datasheet - Page 129
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LFXP3C-3TN100C
Manufacturer Part Number
LFXP3C-3TN100C
Description
FPGA LatticeXP Family 3000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 100-Pin TQFP Tray
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFXP3C-3QN208C.pdf
(130 pages)
Specifications of LFXP3C-3TN100C
Package
100TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
62
Ram Bits
55296
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3TN100C
Manufacturer:
E-SWITCH
Quantity:
14 000
Company:
Part Number:
LFXP3C-3TN100C
Manufacturer:
LATTICE
Quantity:
5 510
Company:
Part Number:
LFXP3C-3TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
www.latticesemi.com
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
November 2007
Revision History
September 2005
February 2005
August 2005
June 2005
April 2005
May 2005
July 2005
July 2005
Date
Version
01.0
01.1
01.2
01.3
02.0
02.1
02.2
03.0
Ordering Information
Pinout Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
DC and Switching
Characteristics
Characteristics
Characteristics
Characteristics
Architecture
Architecture
Architecture
Architecture
Architecture
Introduction
Introduction
Introduction
Section
—
Initial release.
EBR memory support section updated with clarification.
Added TransFR Reconfiguration to Features section.
Added TransFR section.
Added pinout information for LFXP3, LFXP6, LFXP15 and LFXP20.
Updated XP6, XP15 and XP20 EBR SRAM Bits and Block numbers.
Updated Per Quadrant Primary Clock Selection figure.
Added Typical I/O Behavior During Power-up section.
Updated Device Configuration section under Configuration and Testing.
Clarified Hot Socketing Specification
Updated Supply Current (Standby) Table
Updated Initialization Supply Current Table
Added Programming and Erase Flash Supply Current table
Added LVDS Emulation section. Updated LVDS25E Output Termination
Example figure and LVDS25E DC Conditions table.
Updated Differential LVPECL diagram and LVPECL DC Conditions
table.
Deleted 5V Tolerant Input Buffer section. Updated RSDS figure and
RSDS DC Conditions table.
Updated sysCONFIG Port Timing Specifications
Updated JTAG Port Timing Specifications. Added Flash Download
Time table.
Updated Signal Descriptions table.
Updated Logic Signal Connections Dual Function column.
Added lead-free ordering part numbers.
Clarification of Flash Programming Junction Temperature
Added Sleep Mode feature.
Added Sleep Mode section.
Added Sleep Mode Supply Current Table
Added Sleep Mode Timing section
Added SLEEPN and TOE signal names, descriptions and footnotes.
Added SLEEPN and TOE to pinout information and footnotes.
Added footnote 3 to Logic Signal Connections tables for clarification on
emulated LVDS output.
Added clarification of PCI clamp.
Added clarification to SLEEPN Pin Characteristics section.
DC Characteristics, added footnote 4 for clarification. Updated Supply
Current (Sleep Mode), Supply Current (Standby), Initialization Supply
Current, and Programming and Erase Flash Supply Current typical
numbers.
LatticeXP Family Data Sheet
7-1
Change Summary
Revision History
Data Sheet DS1001