74HC595N NXP Semiconductors, 74HC595N Datasheet - Page 2

• Manufacturer Part Number: 74HC595N
• Description: Shift Register Single 8-Bit Serial to Serial/Parallel 16-Pin PDIP Tube
• Manufacturer: NXP Semiconductors

Specifications of 74HC595N

• Package: 16PDIP
• Logic Function: Shift Register
• Logic Family: HC
• Operation Mode: Serial to Serial/Parallel
• Direction Type: Uni-Directional
• Number Of Element Outputs: 9
• Number Of Elements Per Chip: 1
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: -40 to 125 °C
• Output Type: 3-State
• No. Of Elements: 1
• Ic Output Type: Tri State
• Logic Case Style: DIP
• No. Of Pins: 16
• Supply Voltage Range: 2V To 6V
• Operating Temperature Range: -40°C To +125°C
• Svhc: No SVHC
• Logic Type: Shift Register
• Shift Register Function: Serial To Parallel, Serial To Serial
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
FEATURES
APPLICATIONS
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
1998 Jun 04
SYMBOL PARAMETER
t
f
C
C
PHL
max
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typ) shift out frequency
Output capability:
– parallel outputs; bus driver
– serial output; standard
I
Serial-to-parallel data conversion
Remote control holding register.
I
PD
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
CC
P
/t
D
PD
category: MSI.
PLH
= C
f
f
C
V
i
o
is used to determine the dynamic power dissipation (P
CC
= input frequency in MHz
(C
L
= output frequency in MHz
= output load capacitance in pF
PD
L
= supply voltage in V
propagation delay
maximum clock frequency SH
input capacitance
power dissipation capacitance per package
amb
V
SH
ST
MR to Q
V
CC
= 25 C; t
CC
CP
CP
2
2
to Q
to Q
f
o
f
7
i
) = sum of outputs
’
n
7
’
r
= t
(C
I
= GND to V
f
L
= 6 ns.
V
CC
2
CC
f
CP
o
) where:
; for HCT the condition is V
, ST
CP
2
CONDITIONS
C
notes 1 and 2
DESCRIPTION
The 74HC/HCT595 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The “595” is an 8-stage serial shift register with a storage
register and 3-state outputs. The shift register and storage
register have separate clocks.
Data is shifted on the positive-going transitions of the
SH
storage register on a positive-going transition of the ST
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
storage register.
The shift register has a serial input (D
standard output (Q
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.
L
D
= 15 pF; V
CP
in W):
input. The data in each register is transferred to the
I
= GND to V
CC
= 5 V
7
’) for cascading. It is also provided with
CC
HC
16
17
14
100
3.5
115
1.5 V.
74HC/HCT595
TYP.
Product specification
HCT
21
20
19
57
3.5
130
S
) and a serial
UNIT
ns
ns
ns
MHz
pF
pF
CP