EVAL-ADT7463EB ON Semiconductor, EVAL-ADT7463EB Datasheet - Page 3

• Manufacturer Part Number: EVAL-ADT7463EB
• Manufacturer: ON Semiconductor

Specifications of EVAL-ADT7463EB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Parameter
DIGITAL INPUT LOGIC LEVELS
(TACH INPUTS)
DIGITAL INPUT LOGIC LEVELS
(THERM) AGTL+
DIGITAL INPUT CURRENT
SERIAL BUS TIMING
NOTES
1
2
3
4
5
Specifications subject to change without notice.
REV. C
All voltages are measured with respect to GND, unless otherwise specified.
Typicals are at T
Logic inputs accept input high voltages up to V
Timing specifications are tested at logic levels of V
Guaranteed by design, not production tested.
Input High Voltage, V
Input Low Voltage, V
Hysteresis
Input High Voltage, V
Input Low Voltage, V
Input High Current, I
Input Low Current, I
Input Capacitance, C
Clock Frequency, f
Glitch Immunity, t
Bus Free Time, t
Start Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
Detect Clock Low Timeout, t
SDA
SCL
A
= 25°C and represent the most likely parametric norm.
P
t
BUF
BUF
LOW
HIGH
HD;STA
HD;DAT
SW
S
SCLK
SU;STA
SU;DAT
5
IL
IN
IL
IL
IH
IH
IH
t
HD;STA
F
R
t
LOW
TIMEOUT
t
R
MAX
t
HD;DAT
IL
even when the device is operating down to V
= 0.8 V for a falling edge and V
Figure 1. Diagram for Serial Bus Timing
Min
2.0
–0.3
–1
1.3
0.6
0.6
1.3
0.6
100
300
15
t
HIGH
t
F
t
SU;DAT
Typ
0.5
0.75
5
–3–
IH
= 2.0 V for a rising edge.
V
CCP
Max
5.5
+0.8
0.4
+1
400
50
50
1000
300
35
MIN
S
.
t
SU;STA
Unit
V
V
V
V
V p-p
V
V
µA
µA
pF
kHz
ns
µs
µs
µs
µs
µs
ns
µs
ns
ns
ms
t
HD;STA
Test Conditions/Comment
Maximum Input Voltage
Minimum Input Voltage
V
V
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
Can Be Optionally Disabled
IN
IN
= V
= 0
CC
t
SU;STO
P
ADT7463