MAX2820ETM-T Maxim Integrated Products, MAX2820ETM-T Datasheet - Page 16

• Manufacturer Part Number: MAX2820ETM-T
• Description: RF Transceiver 2.4GHz 802.11b Zero-If Transceiver
• Manufacturer: Maxim Integrated Products

Specifications of MAX2820ETM-T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX2820/MAX2820A and MAX2821/MAX2821A
(the MAX2820 family) contain programmable registers
to control various modes of operation for the major cir-
cuit blocks. The registers can be programmed through
the 3-wire SPI/QSPI/MICROWIRE-compatible serial
port. The MAX2820 family includes five programmable
registers:
Each register consists of 16 bits. The four most signifi-
cant bits (MSBs) are the register’s address. The twelve
least significant bits (LSBs) are used for register data.
Table 2 summarizes the register configuration. A
detailed description of each register is provided in
Tables 3–6.
Data is shifted in the MSB first. The data sent to the
transceiver, in 16-bit words, is framed by CSB. When
CSB is low, the clock is active and data is shifted with
the rising edge of the clock. When CSB transitions to
high, the shift register is latched into the register select-
ed by the contents of the address bits. Only the last 16
bits shifted into the device are retained in the shift reg-
ister. No check is made on the number of clock pulses.
Figure 1 documents the serial interface timing for the
MAX2820 family.
2.4GHz 802.11b Zero-IF Transceivers
Table 2. Programming Register Definition Summary (Address and Data)
X = Don’t care.
16
(“A” VERSION)
(“A” VERSION)
REGISTER
1) Test register (always program as in Table 2).
2) Block-enable register
3) Synthesizer register
4) Channel frequency register
5) Receiver settings register
6) Transmitter settings register
TRANSMIT
CHANNEL
RECEIVE
RECEIVE
ENABLE
SYNTH
SYNTH
NAME
______________________________________________________________________________________
TEST
MSB
Programmable Registers
A3
0
0
0
0
0
0
0
0
4 ADDRESS BITS
A2
15
0
0
0
0
0
1
1
1
A1
14
0
0
1
1
1
0
0
0
A0
13
1
0
1
0
0
1
0
0
D11
2C2
2C2
E11
12
0
X
X
X
X
D10
2C1
2C1
E10
11
X
X
X
X
0
2C0
2C0
D9
E9
10
0
X
X
X
X
1C2
1C2
D8
E8
9
0
X
X
X
X
The devices provide power-up loading of default states
for each of the registers. The states are loaded on a
VCC_DIG supply voltage transition from 0V to V
default values are retained until reprogrammed through
the serial interface or the power supply voltage is taken
to 0V. The default state of each register is described in
Table 3. Note: Putting the IC in shutdown mode does
not change the contents of the programming registers.
The block-enable register permits individual control of the
enable state for each major circuit block in the transceiver.
The actual enable condition of the circuit block is a logical
function of the block-enable bit setting and other control
input states. Table 4 documents the logical definition of
state for each major circuit block.
The synthesizer register (SYNTH) controls the reference
frequency divider and charge-pump current of the PLL.
See Table 5 for a description of the bit settings.
The channel frequency register (CHANNEL) sets the
RF carrier frequency for the radio. The channel is pro-
grammed as a number from 0 to 99. The actual frequency
is 2400 + channel in MHz. The default setting is 37 for
2437MHz. See Table 6 for a description of the bit settings.
The receive settings register (RECEIVE) controls the
receive filter -3dB corner frequency, RX level detector
midpoint, and VGA DC offset nulling parameters. The
defaults are intended to provide proper operation.
1C1
1C1
D7
E7
X
X
X
X
8
0
12 DATA BITS
CF6
1C0
1C0
ICP
D6
E6
7
0
X
X
CF5
DL1
D5
E5
R5
R5
Channel Frequency Register
6
0
0
X
Receiver Settings Register
(MAX2820/MAX2821 Only)
Power-Up Default States
CF4
DL0
D4
R4
R4
E4
X
5
0
1
Block-Enable Register
Synthesizer Register
CF3
PA3
D3
R3
R3
E3
SF
4
0
0
BW2
CF2
PA2
D2
R2
R2
E2
3
1
X
BW1
CF1
PA1
D1
E1
R1
R1
X
2
1
CC
. The
BW0
LSB
CF0
PA0
D0
E0
R0
R0
1
X