PI6C3Q993-5QEX Pericom Semiconductor, PI6C3Q993-5QEX Datasheet - Page 7

• Manufacturer Part Number: PI6C3Q993-5QEX
• Description: Phase Locked Loops (PLL) Programmable Skew Zero Delay
• Manufacturer: Pericom Semiconductor
• Type: Programmable PLL Clock Driverr

Specifications of PI6C3Q993-5QEX

• Number Of Circuits: 1
• Maximum Input Frequency: 85 MHz
• Minimum Input Frequency: 3.75 MHz
• Output Frequency Range: 15 MHz to 85 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: QSOP-28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Notes:
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
t
S
S
t
t
t
t
t
t
F
t
t
t
t
S
S
S
S
S
t
O
y
R
K
O
t
O
R
t
t
L
P
N
K
K
K
K
K
D
P
t
P
O
t
m
P
t
E
D
R
F
P
W
R J
W
U
E
E
E
E
E
E
A
O
W
W
W
D
C
S I
C
All timing tolerances apply for F
Skew is the time between the earliest and the latest output transition among all outputs for which the same t
has been selected when all are loaded with the specified load.
t
t
There are 3 classes of outputs: Nominal (multiple of t
and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
t
air flow, etc.)
t
normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t
within specified limits.
t
Measured at 2.0V.
Measured at 0.8V.
Refer to Table10 for more detail.
b
W
W
W
W
W
V
H
L
M
L
SKEWPR
SKEW0
DEV
LOCK
PD
K
H
V
L
P
E
l o
L
0
2
3
4
1
R
09-0003
is measured with REF input rise and fall times (from 0.8V to 2.0V) of 1.0ns.
O
O
O
O
O
O
O
O
O
C
V
R
R
r P
e Z
e Z
D
R
P
is output-to-output skew between any two devices operating under the same conditions (V
is time required before synchronization is achieved. This specification is valid only after V
E
E
E
L
c y
C
t u
t u
t u
t u
e
u
u
u
u
u
g o
o r
o r
i v
p t
p t
p t
p t
p t
L
O
F
F
F
is the skew between outputs when they are selected for 0t
u p
u p
u p
u p
- e l
e c
a r
t u
t u
t u
t u
t u
is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t
o l
e r f
u p
u p
i
u o
o
p n
s t
s t
s t
s t
m
o t
t u
t -
k c
u d
H
L
s i r
a f
e s l
e s l
u q
p t
t u
m
e k
e k
e k
e k
- o
c -
u p
O
G I
t l l
t u
y t
t e
t
b a
n e
m i
c y
w
w
w
w
e d
o t
W
s t
w
w
m i
H
m i
m
c
y c
e l
e l
d i
d i
e
i v
e k
(
(
(
(
F
c y
e
t
(
t a
s i r
s i r
s i r
s i r
t
h t
h t
m i
e
1 1
e c
s
B
m i
1 (
u o
1 (
r
w
e l
e k
h c
- e
- e
- e
- e
) 1
1 ,
n a
e
H
L
e
) 1
r p
p t
s
) 7
d e
v
w
l a (
O
s i r
a f
s i r
a f
e g
e k
e d
G I
e d
p o
r a
t u
, l l
, l l
W
p -
o l
, e
, e
t
w
i t a
i v
H
m i
i v
g a
t i j
o n
o n
2 (
i a
1 (
i t a
i t a
2 (
t u
a f
a f
n o
e
r e t
, 1
i t a
) 1
s r
) 1
D
u p
- l l
m
- l l
m
n o
n o
u
2 1
n o
1 (
f
Table 9. Switching Characteristics Over Operating Range
t i n
n i
n i
e
e k
a f
a f
o r
) s t
1 ,
) 1
c s
f
- l a
l a
f
, l l
, l l
o r
) 6
o r
w
m
d
d -
i r
C
l e
a s
n i
f i d
m
m
x (
0 5
t p
i v i
L
y a
e v
NOM
m
0 5
r e f
Q
0 5
o i
=
e d
%
e t r
(
e
1 1
, 0
%
n
n e
p 0
%
1 (
c
, d
1 ,
, d
a l
) 1
(
x
c t
(
) 8
1 1
F
1 1
≥ 25MHz. Guaranteed by design and characterization.
d
Q
s s
d
(
2 ,
v i
1 ,
1 1
a l
v i
) 1
) 0
o
d i
) 9
s s
1 ,
d i
1 (
t u
d e
) 4
d e
, 1
o
u p
2 1
t u
d -
i
R
e P
) s t
v n
u p
1 ,
M
v i
) 3
k a
(
t r e
1 1
) s t
d i
S
1 ,
t -
d e
d e
(
1 1
) 5
- o
(
(
1 ,
1 1
1 1
e p
) 5
1 ,
U
1 ,
k a
) 5
) 5
delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH),
–
M
1 –
. 0
. 0
3
3
. 0
3.3V Programmable Skew PLL Clock Driver SuperClock
0 .
0 .
5 1
5 1
. n i
5 2
2 .
P
P
6 I
6 I
s
s
U
7
e e
e e
.
C
C
3
3
T
. 0
. 0
. 0
. 0
. 0
T
T
0
1
1
Q
Q
y
b a
b a
0
0
5 0
5 2
0 3
5 2
0 5
1 .
0 .
0 .
. p
9
9
e l
e l
1 9
3 9
2
3
2 -
2 -
M
. 0
. 0
. 0
. 0
. 0
. 0
. 0
2
1
1
2
1
1
1
0
5 2
0 0
a
0 2
5 2
0 5
0 5
0 9
5 7
5 2
0 .
5 .
2 .
2 .
5 .
5 .
5 .
. x
M
0 –
1 –
. 0
. 0
3
3
0 .
0 .
5 1
5 1
. n i
5 .
2 .
P
P
6 I
6 I
s
s
e e
e e
C
C
CC
T
. 0
3
3
0
0
0
0
0
1
1
T
T
y
0
0
Q
Q
5 2
6 .
5 .
5 .
5 .
b a
b a
1 .
0 .
0 .
CC
. p
is stable & within
9
9
e l
e l
1 9
3 9
, ambient temperature,
2
3
5 -
5 -
M
. 0
. 1
2
0
0
0
0
2
3
0
1
1
1
1
1
0 4
U
0 0
a
5 2
5 .
7 .
2 .
7 .
0 .
5 2
5 .
2 .
5 .
0 .
5 .
5 .
5 .
.
. x
PI6C3Q991, PI6C3Q993
U
delay
M
0 –
1 –
. 0
. 0
3
3
0 .
0 .
5 1
5 1
. n i
7 .
2 .
P
P
s
6 I
6 I
e e
PD
T
C
C
0
0
0
1
0
1
1
1
y
T
s
0
0
3 .
6 .
7 .
3
3
1 .
0 .
2 .
5 .
5 .
e e
is
. p
b a
PS8449H
Q
Q
e l
9
9
T
1 9
3 9
b a
2
M
e l
. 0
. 0
. 1
2
1
1
1
1
0
1
3
3
2
2
0
0 4
3
0 0
a
5 2
5 7
0 .
5 .
2 .
7 .
5 6
7 .
2 .
0 .
5 .
5 .
5 .
5 .
. x
10/27/09
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