AX5131-TSSOP20-TU AXSEM, AX5131-TSSOP20-TU Datasheet - Page 21

• Manufacturer Part Number: AX5131-TSSOP20-TU
• Description: RF Transmitter TSSOP-Class-IC
• Manufacturer: AXSEM
• Type: Single Chip Transceiverr

Specifications of AX5131-TSSOP20-TU

• Package / Case: TSSOP-20
• Operating Frequency: 400 MHz to 940 MHz
• Maximum Operating Temperature: + 60 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.2 V to 3.6 V
• Supply Current: 100 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.8.
Most radio systems today group data into packets. The framing unit is responsible for
converting these packets into a bit-stream suitable for the modulator.
The Framing unit supports four different modes:
The micro-controller communicates with the framing unit through a 32 level × 10 bit FIFO. The
FIFO decouples micro-controller timing from the radio (modulator) timing. The bottom 8 bits
of the FIFO contain transmit data. The top 2 bit are used to convey meta information in HDLC
and 802.15.4 modes. They are unused in Raw mode. The meta information consists of packet
begin / end information and the result of CRC checks. The FIFO can be written in power-
down mode.
The FIFO can be operated in polled or interrupt driven modes. In polled mode, the micro-
controller must periodically read the FIFO status register or the FIFO count register to
determine whether the FIFO needs servicing.
In interrupt mode EMPTY, NOT EMPTY, FULL, NOT FULL and programmable level interrupts are
provided. The
is level triggered, active high. Interrupts are acknowledged by removing the cause for the
interrupt, i.e. by emptying or filling the FIFO.
Basic FIFO status (EMPTY, FULL, Overrun, Underrun, and the top two bits of the top FIFO word)
are also provided during each SPI access on MISO while the micro-controller shifts out the
register address on MOSI. See the SPI interface section for details. This feature significantly
reduces the number of SPI accesses necessary.
Version 1.0
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Framing and FIFO
HDLC
Raw
802.15.4 compliant
AX5131
signals interrupts by asserting (driving high) its IRQ line. The interrupt line
Circuit Description
Datasheet AX5131
21