PI6C2952FBE Pericom Semiconductor, PI6C2952FBE Datasheet

PI6C2952FBE

Manufacturer Part Number

PI6C2952FBE

Description

Phase Locked Loops (PLL) 180MHZ 3Bank 11Output ZDB

Manufacturer

Pericom Semiconductor

Type

Zero Delay PLL Clock Driverr

Datasheets

1.PI6C2952.pdf (6 pages)

2.PI6C2952FBE.pdf (6 pages)

Specifications of PI6C2952FBE

Number Of Circuits

Output Frequency Range

180 MHz

Supply Voltage (max)

3.465 V

Supply Voltage (min)

3.135 V

Maximum Operating Temperature

+ 70 C

Minimum Operating Temperature

0 C

Mounting Style

SMD/SMT

Operating Supply Voltage

3.3 V

Package / Case

LQFP-32

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

PI6C2952FBEX

Manufacturer:

PERICOM

Quantity:

20 000

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Features

• ±100ps Cycle-to-Cycle Jitter

• Fully Integrated PLL

• Output Frequency up to 180MHz

• High-Impedance Disabled Outputs

• Compatible with PowerPC, Intel, and High-Performance

• Configurable Output Frequency

• 32-Pin LQFP Package (FB)

Pin Configuration

RISC Microprocessors

GNDO

VCCO

Qb2

Qb3

Qc0

Qc1

24 23 22 21 20 19 18 17

2 3 4

32-Pin

6 7 8

VCCO

Qa2

Qa1

GNDO

Qa0

VCCI

VCCA

PLL_En

Description

The PI6C2952 is a 3.3V compatible, PLL-based clock driver device

targeted for high-performance clock applications. The device fea-

tures a fully integrated PLL with no external components

required. With output frequencies up to 180MHz and eleven low-

skew outputs, the PI6C2952 is well suited for high-performance

designs. The device employs a fully differential PLL design to

optimize jitter and noise rejection performance.

The PI6C2952 features three banks of individually configurable

outputs. The banks contain 5 outputs, 4 outputs, and 2 outputs. The

internal divide circuitry allows for output frequency ratios of 1:1, 2:1,

3:1, and 3:2:1. The output frequency relationship is controlled by the

fsel frequency control pins. The fsel pins and other inputs are

LVCMOS/LVTTL compatible inputs.

The PI6C2952 uses external feedback to the PLL. This features

allows the device to be used as a “zero delay” buffer. Any of the

eleven outputs can be used as feedback to the PLL. To optimize PLL

stability and jitter performance,the VCO_Sel pin allows for the

choice of two VCO ranges. For board level test, the MR/OE pin

allows a user to force the outputs into high impedance. For system

debug, the PI6C2952’s PLL can be bypassed. When forced to a logic

HIGH, the PL_LEN input routes the signal on the RefClk input

around the PLL directly to the internal dividers. Because the signal

is routed through the dividers, it may take several transitions of the

RefClk to affect a transition on the outputs. This features allows a

designer to single step the design for debug purposes.

The PI6C2952’s outputs are LVCMOS which are optimally designed

to drive terminated transmission lines. For applications using series-

terminated transmission lines, each PI6C2952 output can drive two

lines. This capability provides an effective fanout of 22, more than

enough clocks for most clock tree designs.

Low Voltage PLL Clock Driver

PI6C2952

PS8542A

01/30-06

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