PI6CV855LEX Pericom Semiconductor, PI6CV855LEX Datasheet

PI6CV855LEX

Manufacturer Part Number

PI6CV855LEX

Description

Phase Locked Loops (PLL) 170 MHZ 1:10 SSTV Clock Driver

Manufacturer

Pericom Semiconductor

Type

Zero Delay PLL Clock Driverr

Datasheet

1.PI6CV855LE.pdf (9 pages)

Specifications of PI6CV855LEX

Number Of Circuits

Maximum Input Frequency

170 MHz

Minimum Input Frequency

60 MHz

Output Frequency Range

60 MHz to 170 MHz

Supply Voltage (max)

2.7 V

Supply Voltage (min)

2.3 V

Maximum Operating Temperature

+ 70 C

Minimum Operating Temperature

0 C

Mounting Style

SMD/SMT

Operating Supply Voltage

2.5 V

Package / Case

TSSOP-28

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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Block Diagram

Features

• PLL clock distribution optimized for SSTL_2 DDR SDRAM

• Distributes one differential clock input pair to five differential

• Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2

• Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2

• External feedback pins (FBIN,FBIN) are used to

• Operates at AV

• Packaging (Pb-free & Green available):

CLK

FBIN

applications.

clock output pairs.

synchronize the outputs to the input clocks.

and V

– 28-pin TSSOP (L)

08-0298

DDQ

= 2.5V for differential output drivers

= 2.5V for core circuit and internal PLL,

Test Ciruit

PLL

Logic

and

FBOUT

Description

PI6CV855 PLL clock device is developed for SSTL_DDR SDRAM

applications. This PLL Clock Buffer is designed for 2.5 V

2.5V AV

The device is a zero delay buffer that distributes a differential clock

input pair (CLK, CLK) to five differential pairs of clock outputs

(Y[0:4], Y[0:4]) and one differential pair feedback clock outputs

(FBOUT, FBOUT). The clock outputs are controlled by the input

clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the

Analog Power input (AV

PLL is turned off and bypassed for test purposes.

The PI6CV855 is able to track Spread Spectrum Clocking to reduce

EMI.

Pin Configuration

operation and differential data input and output levels.

V DDQ

AGND

AV DD

SSTL 2 DDR SDRAM Memory

GND

CLK

PLL Clock Driver for 2.5V

). When the AV

28-Pin

V DDQ

GND

FBOUT

V DDQ

FBIN

GND

V DDQ

GND

is strapped low, the

PI6CV855

PS8545D

DDQ

11/12/08

and

Related parts for PI6CV855LEX

PI6CV855LEX Summary of contents

Page 1

Features • PLL clock distribution optimized for SSTL_2 DDR SDRAM applications. • Distributes one differential clock input pair to five differential clock output pairs. • Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 • Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 • External feedback ...

Page 2

Pinout Table ...

Page 3

Absolute Maximum Ratings ...

Page 4

DC Specifications Recommended Operating Conditions ...

Page 5

AC Specifications Switching characteristics over recommended operating free-air temperature range, f (See Figure 1 and θ ...

Page 6

DDQ /2 V DDQ /2 08-0298 Z = 60W R =120W Z = 60W Figure 1. IBIS Model Output Load C=14pF V DDQ /2 C=14pF V DDQ /2 Figure 2. Output Load Test Circuit 6 PI6CV855 PLL ...

Page 7

CLK CLK FBIN FBIN Yx Yx Yx, FBOUT Yx, FBOUT 08-0298 t t cycle n cycle n jit(cc) cycle ...

Page 8

Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT 80% 20% Clock Inputs and Outputs 08-0298 t cycle jit(per) cycle n Figure 6. Period Jitter t half period n half ...

Page 9

... Package Outline Exclusive of Mold Flash and Metal Burr 2. Controlling dimentions in millimeters 3. Ref: JEDEC MO-153F/AE Ordering Information Ordering Code PI6CV855LE Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 08-0298 .169 4.3 .177 4.5 .047 1.20 Max SEATING PLANE ...

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