ATA5428-PLQW80 Atmel, ATA5428-PLQW80 Datasheet - Page 31
ATA5428-PLQW80
Manufacturer Part Number
ATA5428-PLQW80
Description
RF Transceiver ASK/FSK Transceiver 434 and 868MHz
Manufacturer
Atmel
Datasheet
1.ATAB5428-8-WB.pdf
(100 pages)
Specifications of ATA5428-PLQW80
Wireless Frequency
226 KHz, 237 KHz
Interface Type
4-Wire SPI
Noise Figure
7 dB
Output Power
10 dBm
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-48
Maximum Data Rate
20 Kbps
Minimum Operating Temperature
- 40 C
Modulation
ASK, FSK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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4841D–WIRE–10/07
AVCC is the internal operation voltage of the RF transceiver and is fed by VS1 via the switch
SW_AVCC. AVCC must be blocked with a 68 nF capacitor (see
on page 8
DVCC is the internal operation voltage of the digital control logic and is fed by VS1 or VSOUT
via the switch SW_DVCC. DVCC must be blocked on pin DVCC with 68 nF (see
page
Pin VSOUT is a power supply output voltage for external devices (for example, microcontrollers)
and is fed by VS1 via the switch SW_VSOUT, or by the auxiliary voltage supply VAUX via
V_REG2. The voltage regulator V_REG2 regulates VSOUT to typically 3.25V. If the voltage reg-
ulator is active, a blocking capacitor of 2.2 µF has to be connected to VSOUT. VSOUT can be
switched off by the VSOUT_EN bit in control register 3 and is then reactivated by conditions
found in
Pin N_RESET is set to low if the voltage V
can be used as a reset signal for a connected microcontroller (see
Figure 5-4 on page
Pin PWR_ON is an input to switch on the transceiver (active high).
Pin T1 to T5 are inputs for push buttons and can also be used to switch on the transceiver
(active low).
For current consumption reasons it is recommended to set T1 to T5 to GND, or PWR_ON to
VCC only temporarily. Otherwise, an additional current flows because of a 50 k pull-up resistor.
There are two voltage monitors generating the following signals (see
• DVCC_OK if DVCC > 1.5V typically
• VSOUT_OK if VSOUT > V
• Low_Batt if VSOUT < V
7,
Figure 2.2 on page 8
Figure 5-2 on page
and
Figure 2-3 on page
35).
ATA5423/ATA5425/ATA5428/ATA5429
Thres2
32.
and
Thres1
(2.38V typically)
Figure 2-3 on page
9).
(2.3V typically)
VSOUT
at pin VSOUT drops below 2.3V (typically) and
9).
Figure 2-1 on page
Figure 5-3 on page 34
Figure 5-1 on page
Figure 2-1 on
7,
Figure 2.2
30):
and
31
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