MAX7032ATJ+T Maxim Integrated Products, MAX7032ATJ+T Datasheet - Page 19

• Manufacturer Part Number: MAX7032ATJ+T
• Description: RF Receiver IC TRASCEIVER ASK/FSK
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of MAX7032ATJ+T

• Package / Case: TQFN-32 EP
• Operating Frequency: 450 MHz
• Operating Supply Voltage: 2.7 V, 5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3. Register Summary
REGISTER A[5:0]
ASK/FSK Transceiver with Fractional-N PLL
0x0C
0x0D
0x0A
0x0B
0x0E
0x1A
0x00
0x01
0x02
0x03
0x05
0x06
0x07
0x08
0x09
0x0F
0x10
Low-Cost, Crystal-Based, Programmable,
______________________________________________________________________________________
Power configuration
Control
Configuration0
Configuration1
Oscillator frequency
Off timer—t
Off timer—t
CPU recovery timer—t
RF settling timer—t
byte)
RF settling timer—t
byte)
On timer—t
On timer—t
Transmitter low-frequency
setting—TxLOW (upper byte)
Transmitter low-frequency
setting—TxLOW (lower byte)
Transmitter high-frequency
setting—TxHIGH (upper byte)
Transmitter high-frequency
setting—TxHIGH (lower byte)
Status register (read only)
REGISTER NAME
OFF
OFF
ON
ON
(upper byte)
(lower byte)
(upper byte)
(lower byte)
RF
RF
(upper
(lower
CPU
Enables/disables the LNA, AGC, mixer, baseband, peak
detectors, PA, and RSSI output (see Table 5).
Controls AGC lock, gain state, peak-detector tracking, polling
timer and FSK calibration, clock signal output, and sleep mode
(see Table 6).
Sets options for modulation, TX/RX mode, manual-gain mode,
discontinuous receive mode, off-timer and on-timer prescalers
(see Table 7).
Sets options for automatic FSK calibration, clock output, output
clock divider ratio, AGC dwell timer (see Tables 8, 10, 11, and 12).
Sets the internal clock frequency divisor. This register must be set
to the integer result of f
Register (Address 0x05) section).
Sets the duration that the MAX7032 remains in low-power mode
when DRX is active (see Table 12).
Increases maximum time the MAX7032 stays in lower power mode
while CPU wakes up when DRX is active (see Table 13).
During the time set by the RF settling timer, the MAX7032 is
powered on with the peak detectors and the data outputs disabled
to allow time for the RF section to settle. DIO must be driven low at
any time during t
restarts (see Table 14).
Sets the duration that the MAX7032 remains in active mode when
DRX is active (see Table 15).
Sets the low frequency (FSK) of the transmitter or the carrier
frequency of ASK for the fractional-N synthesizer.
Sets the high frequency (FSK) of the transmitter for the fractional-N
synthesizer.
Provides status for PLL lock, AGC state, crystal operation, polling
timer, and FSK calibration (see Table 9).
LOW
= t
XTAL
CPU
DESCRIPTION
/100kHz (see the Oscillator Frequency
+ t
RF
+ t
ON
or the timer sequence
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