ATA5824-PLQW80 Atmel, ATA5824-PLQW80 Datasheet - Page 44
![RF Transceiver RF Data Control Duplex Trans.](/photos/30/99/309912/qfn-48_sml.jpg)
ATA5824-PLQW80
Manufacturer Part Number
ATA5824-PLQW80
Description
RF Transceiver RF Data Control Duplex Trans.
Manufacturer
Atmel
Datasheet
1.ATA5824-PLQW.pdf
(98 pages)
Specifications of ATA5824-PLQW80
Wireless Frequency
435 MHz
Interface Type
4-Wire SPI
Noise Figure
6.5 dB
Output Power
10 dBm
Operating Supply Voltage
4.4 V to 5.25 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
QFN-48
Maximum Data Rate
5 Kbps
Minimum Operating Temperature
- 40 C
Modulation
ASK, FSK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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12.4
44
Pin N_PWR_ON
ATA5823/ATA5824
(Status register)
To switch the transceiver from OFF to IDLE mode, pin N_PWR_ON must be set to 0 (maximum
0.2
tive edge and switches on DVCC and AVCC.
If V
sets the status bit N_Power_On to 1, an interrupt is issued (T
on pin CLK is available.
If the level on pin N_PWR_ON was set to 1 before the interrupt is issued, the transceiver stays in
OFF mode.
Note:
Figure 12-2. Timing Pin N_PWR_ON, Status Bit N_Power_On
N_POWER_ON
If the transceiver is in any of the active modes (IDLE, TX, RX, RX_Polling, FD), an integrated
debounce logic is active. If there is an event on pin N_PWR_ON, a debounce counter is set to 0
(T = 0) and started. The status is updated, an interrupt is issued and the debounce counter is
stopped after reaching the counter value T = 8195
An event on N_PWR_ON before reaching T = 8195
While the debounce counter is running, the bit CLK_ON in control register 3 is set to 1.
The interrupt is deleted after reading the status register or executes the command Delete_IRQ.
If pin N_PWR_ON is not used, it can be left open because of an internal pull-up resistor (typi-
cally 50 k ).
DVCC, AVCC
N_PWR_ON
DVCC
V
VS2
It is not possible to set the transceiver to OFF-mode by setting pin N_PWR_ON to 1. If pin
N_PWR_ON is not used, it should be left open because of the internal pull-up resistor
exceeds 1.6V (typically) and the XTO is settled, the digital control logic is active and
CLK
IRQ
) for at least T
1.6V (typ)
OFF Mode
N_PWR_ON_IRQ
T
N_PWR_ON_IRQ
(see
IDLE Mode
Figure
12-2). The transceiver recognizes the nega-
T
DCLK
T
DCLK
.
stops the debounce counter.
N_PWR_ON_IRQ
) and the output clock
4829D–RKE–06/06
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