PE43502MLI-Z Peregrine Semiconductor, PE43502MLI-Z Datasheet
PE43502MLI-Z
Specifications of PE43502MLI-Z
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PE43502MLI-Z Summary of contents
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... PE43502 50 Ω RF Digital Attenuator 5-bit, 15.5 dB, 9 kHz - 6 GHz Features RF Output P/S ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. HaRP™-enhanced UltraCMOS™ device Attenuation: 0.5 dB steps to 15.5-dB High Linearity: Typical +58 dBm IP3 Excellent low-frequency performance 3 5.0 V Power Supply Voltage ...
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... Frequency (GHz) ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 3 5 Frequency 9 kHz ≤ 6 GHz 9 kHz < 4 GHz 4 GHz ≤ 6 GHz 4 GHz ≤ 6 GHz 4 GHz ≤ 6 GHz 9 kHz - 6 GHz All States 9 kHz - 6 GHz Input ...
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... Document No. 70-0247-06 │ www.psemi.com Figure 8. Input Return Loss vs. Attenuation +85C Figure 10. Relative Phase vs. Frequency 1dB 2dB 15.5dB Figure 12. Input IP3 vs. Frequency +85C ©2008-2009 Peregrine Semiconductor Corp. All rights reserved +25C 0dB 0.5dB 1dB 4dB 8dB 15.5dB 0 -5 -10 -15 -20 -25 -30 -35 - Frequency (GHz) 0dB 0 ...
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... The PE43503 has a maximum 25 kHz switching rate. Switching rate is defined to be the speed at which the DSA can be toggled across attenuation states. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page Table 3. Operating Ranges Parameter Min V Power Supply Voltage 3 ...
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... Attenuation Word: Multiply by 4 and convert to binary → 12.5 dB → 50 → 00110010 Serial Input: 00110010 Document No. 70-0247-06 │ www.psemi.com Table 8. Attenuation Word Truth Table Function Attenuation Setting RF1-RF2 Reference I.L. 0 15.5 dB LSB (first in Bits must be set to logic low ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Attenuation Word Attenuation (LSB Reference I. ...
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... Serial data is clocked in LSB first. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA ...
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... T 100 - ns 100 - ns 100 - ns 100 - ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. T DIH T PSIH T LESU T LEPW T PD VALID Characteristics < 85° C, unless otherwise specified A Parameter Min Latch Enable minimum LEPW pulse width Parallel data setup time DISU T Parallel data hold time ...
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... Parallel is selected in the software. For manual latched-parallel programming, the procedure is identical to direct-parallel except now the LE pin on the Serial header must be logic low ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page Figure 17. Evaluation Board Layout Peregrine Specification 101-0310 Note: Reference Figure 18 for Evaluation Board Schematic as the parallel bits are applied ...
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... DSA 50 Ohm 4x4 MLP24 5 RF1 J4 6 GND Z=50 Ohm SMA 1 Note: Capacitors C1-C8, C13, & C14 may be omitted. SERIAL HEADER 4 CLK 1 CLOCK DATA 2 DATA GND CLK GND J5 14 RF2 SMA 13 1 GND Z=50 Ohm ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page ...
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... YYWW ZZZZZ YYWW = Date Code ZZZZZ = Last five digits of Lot Number Table 12. Ordering Information Order Code Part Marking PE43502MLI 43502 PE43502G-24QFN 4x4mm-75A PE43502MLI-Z 43502 PE43502G-24QFN 4x4mm-3000C EK43502-01 PE43502 -EK ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page Tape Feed Direction A = 4.35 ...
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... Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page ...