PE43703MLI-Z Peregrine Semiconductor, PE43703MLI-Z Datasheet - Page 11

• Manufacturer Part Number: PE43703MLI-Z
• Description: IC RF DSA 7BIT 50 OHM 32-QFN
• Manufacturer: Peregrine Semiconductor
• Series: UltraCMOS™, HaRP™r

Specifications of PE43703MLI-Z

• Attenuation Value: 31.75dB
• Tolerance: ±0.25dB
• Frequency Range: 9kHz ~ 6GHz
• Power (watts): *
• Impedance: 50 Ohm
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1046-1048-2

PE43703
Product Specification
Figure 29. Serial-Addressable Timing Diagram
Figure 30. Latched-Parallel/Direct-Parallel Timing Diagram
Table 13. Serial-Addressable Interface
V
Document No. 70-0245-05 │ www.psemi.com
ADD[2:0]
Symbol
DO[6:0]
DO[6:0]
DD
DI[6:0]
DI[6:0]
T
T
T
T
T
T
T
F
T
T
T
T
T
T
CLK
LEPW
CLKH
LESU
PSSU
= 3.3 or 5.0 V, -40° C < T
CLKL
SISU
DISU
P/S
CLK
ASU
PSH
SIH
DIH
AH
PD
LE
SI
P/S
LE
T
SISU
Serial clock frequency
Serial clock HIGH time
Serial clock LOW time
Last serial clock rising edge
setup time to Latch Enable
rising edge
Latch Enable min. pulse width
Serial data setup time
Serial data hold time
Parallel data setup time
Parallel data hold time
Address setup time
Address hold time
Parallel/Serial setup time
Parallel/Serial hold time
Digital register delay (internal)
T
AC Characteristics
T
VALID
PSSU
DISU
T
T
ASU
SIH
D[0]
T
PSSU
Parameter
D[1]
T
CLKL
T
DIPD
VALID
T
DISU
T
D[2]
A
LEPW
< 85° C, unless otherwise specified
D[3]
VALID
T
PD
T
PSH
Min
100
100
100
100
100
100
T
D[4]
30
30
10
30
10
10
DIH
-
-
T
CLKH
Max
D[5]
10
10
-
-
-
-
-
-
-
-
-
-
-
-
D[6]
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bits can either be set to logic high or logic low
D[7] must be set to logic low
D[7]
A[0]
Table 14. Parallel and Direct Interface
V
DD
Symbol
A[1]
= 3.3 or 5.0 V, -40° C < T
T
T
T
T
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
T
T
T
LEPW
PSSU
DISU
DIPD
PSIH
DIH
PD
A[2]
AC Characteristics
Latch Enable minimum
pulse width
Parallel data setup time
Parallel data hold time
Parallel/Serial setup time
Parallel/Serial hold time
Digital register delay
(internal)
Digital register delay
(internal, direct mode only)
Parameter
A
< 85° C, unless otherwise specified
Min
100
100
100
100
30
-
-
T
LESU
Page 11 of 15
T
Max
LEPW
10
5
-
-
-
-
-
T
T
T
DIH
AIH
PSIH
Unit
VALID
ns
ns
ns
ns
ns
ns
ns
T
PD