NCP1252ADR2G ON Semiconductor, NCP1252ADR2G Datasheet - Page 14

• Manufacturer Part Number: NCP1252ADR2G
• Description: IC PWM CTLR CURRENT MODE 8-SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1252ADR2G

• Frequency - Max: 500kHz
• Pwm Type: Current Mode
• Number Of Outputs: 1
• Duty Cycle: 50%
• Voltage - Supply: 9 V ~ 28 V
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -25°C ~ 125°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Duty Cycle (max): 48 %
• Mounting Style: SMD/SMT
• Switching Frequency: 92 KHz to 550 KHz
• Maximum Operating Temperature: + 125 C
• Fall Time: 22 ns
• Rise Time: 26 ns
• Synchronous Pin: No
• Topology: Flyback, Forward
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

substituting Equation 4 into Equation 3 as follow:
can be calculated:
Shut Down
possibility consists at grounding the BO pin as illustrated in
Figure 34.
Ramp Compensation
subharmonic oscillations. These oscillations take place at
half of the switching frequency and occur only during
R
From Equation 4 and Equation 5, the resistor divider value
There is one possibility to shut down the controller; this
Ramp compensation is a known mean to cure
R
R
BOup
BOlo
BOup
+ 1
+ 370 * 350
can be also written independently of R
R
10 m
BOlo
10 m
R
370 * 1
350 * 1
+
BOup
V
I
BO
BO
+
+ 2.0 MW
V
* 1 + 5731 W
V
V
bulkon
bulkon
bulkoff
I
* V
BO
* V
* V
bulkoff
BO
BO
Figure 35. Short Circuit Detection Example
* 1
BOlo
(eq. 4)
(eq. 5)
http://onsemi.com
by
Fault timer: 15 ms
14
Short Circuit or Over Load Protection:
the CS pin level reaching its maximum level at 1 V. In that
case the fault status is stored in the latch and allows the
digital timer count. If the digital timer ends then the fault is
latched and the controller permanently stops the pulses on
the driver pin.
timer is reset only after 3 switching controller periods
without fault detection (or when the CS pin < 1 V during at
least 3 switching periods).
reset is sensed or if V
Continuous Conduction Mode (CCM) with a duty−cycle
close to and above 50%. To lower the current loop gain, one
usually injects between 50 and 100% of the inductor
downslope. depicts how internally the ramp is generated:
internal oscillator ramp buffered. A switch placed between
the buffered internal oscillator ramp and R
the ramp compensation during the OFF time DRV signal.
Short Circuit
A short circuit or an overload situation is detected when
If the fault is gone before ending the digital timer, the
If the fault is latched the controller can be reset if a BO
The ramp compensation applied on CS pin is from the
CC
is cycled down to V
CS pin
(500 mV/div)
12 Vout
(5 V/div)
Time
(4 ms/div)
ramp
CC(off)
disconnects
.