LFEC1E-4TN144C LATTICE SEMICONDUCTOR, LFEC1E-4TN144C Datasheet - Page 15
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LFEC1E-4TN144C
Manufacturer Part Number
LFEC1E-4TN144C
Description
FPGA LatticeEC Family 1500 Cells 378MHz 130nm (CMOS) Technology 1.2V 144-Pin TQFP
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC1E-4TN144C
Package
144TQFP
Family Name
LatticeEC
Device Logic Units
1500
Maximum Internal Frequency
378 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
97
Ram Bits
18432
In System Programmability
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC1E-4TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-14. DCS Waveforms
sysMEM Memory
The LatticeECP/EC devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of a 9-
Kbit RAM, with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-6.
Table 2-6. sysMEM Block Configurations
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
ROM.
SEL
CLK0
DCSOUT
CLK1
Single Port
True Dual Port
Pseudo Dual Port
Memory Mode
2-12
Configurations
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
256 x 36
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
512 x 18
LatticeECP/EC Family Data Sheet
Architecture
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