CY8C3866LTI-068 Cypress Semiconductor Corp, CY8C3866LTI-068 Datasheet - Page 23

• Manufacturer Part Number: CY8C3866LTI-068
• Description: PSOC 3 QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C38xxr

Specifications of CY8C3866LTI-068

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 25
• Eeprom Size: 2K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 2x20b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Core Size: 8-Bit
• Processor Series: CY8C38
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 25
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 67MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.6 External Memory Interface
CY8C38 provides an EMIF for connecting to external memory
devices. The connection allows read and write accesses to
external memories. The EMIF operates in conjunction with
UDBs, I/O ports, and other hardware to generate external
memory address and control signals. At 33 MHz, each memory
access cycle takes four bus clock cycles.
block diagram. The EMIF supports synchronous and
asynchronous memories. The CY8C38 supports only one type
of external memory device at a time. External memory can be
accessed through the 8051 xdata space; up to 24 address bits
can be used. See
memory can be 8 or 16 bits wide.
Document Number: 001-11729 Rev. *R
PHUB
“xdata Space”
Data,
and Control
Signals
Data,
Signals
Data,
and Control
Signals
Address,
Address,
and Control
Address,
section on page 25. The
Figure 5-1
IO IF
EM Control
Signals
Figure 5-1. EMIF Block Diagram
is the EMIF
EMIF
UDB
Data Signals
Address Signals
Control Signals
Signals
Other
Control
DSI to Port
Control
DSI Dynamic Output
PORTs
PORTs
PORTs
I/O
I/O
I/O
PSoC
External _ MEM_ ADDR [23:0]
External _ MEM_ DATA[15:0]
®
3: CY8C38 Family
Control
Data Sheet
Page 23 of 129
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