XCV100E-6FG256I Xilinx Inc, XCV100E-6FG256I Datasheet - Page 4
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XCV100E-6FG256I
Manufacturer Part Number
XCV100E-6FG256I
Description
FPGA Virtex™-E Family 32.4K Gates 2700 Cells 357MHz 0.18um (CMOS) Technology 1.8V 256-Pin FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Specifications of XCV100E-6FG256I
Package
256FBGA
Family Name
VirtexÂ-E
Device Logic Gates
32400
Device Logic Units
2700
Device System Gates
128236
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
176
Ram Bits
81920
Number Of Logic Elements/cells
2700
Number Of Labs/clbs
600
Total Ram Bits
81920
Number Of I /o
176
Number Of Gates
128236
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Virtex™-E 1.8 V Field Programmable Gate Arrays
Virtex-E Ordering Information
Revision History
The following table shows the revision history for this document.
Module 1 of 4
4
12/7/99
1/10/00
1/28/00
2/29/00
5/23/00
7/10/00
9/20/00
8/1/00
Date
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Example: XCV300E-6PQ240C
Device Type
Speed Grade
(-6, -7, -8)
•
•
•
•
•
•
•
•
•
•
•
•
Initial Xilinx release.
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, T
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
Updated pinout tables, V
Correction to table on p. 22.
Numerous minor edits.
Data sheet upgraded to Preliminary.
Preview -8 numbers added to Virtex-E Electrical Characteristics tables.
Reformatted entire document to follow new style guidelines.
Changed speed grade values in tables on pages 35-37.
Min values added to Virtex-E Electrical Characteristics tables.
XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).
Corrected user I/O count for XCV100E device in Table 1 (Module 1).
Changed several pins to “No Connect in the XCV100E“ and removed duplicate V
pins in Table ~ (Module 4).
Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4).
Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4).
Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“.
Figure 1: Ordering Information
www.xilinx.com
1-800-255-7778
CC
page 20, and corrected Figure 20.
BYP
Temperature Range
C = Commercial (Tj = 0 C to +85 C)
Number of Pins
Package Type
BG = Ball Grid Array
FG = Fine Pitch Ball Grid Array
HQ = High Heat Dissipation
I = Industrial (Tj = -40 C to +100 C)
values, buffered Hex Line info, p. 8, I/O Timing
Revision
DS022_043_072000
Production Product Specification
DS022-1 (v2.3) July 17, 2002
CCINT
R