XCV100E-6FG256I Xilinx Inc, XCV100E-6FG256I Datasheet - Page 22

• Manufacturer Part Number: XCV100E-6FG256I
• Description: FPGA Virtex™-E Family 32.4K Gates 2700 Cells 357MHz 0.18um (CMOS) Technology 1.8V 256-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV100E-6FG256I

• Package: 256FBGA
• Family Name: Virtex™-E
• Device Logic Gates: 32400
• Device Logic Units: 2700
• Device System Gates: 128236
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 176
• Ram Bits: 81920
• Number Of Logic Elements/cells: 2700
• Number Of Labs/clbs: 600
• Total Ram Bits: 81920
• Number Of I /o: 176
• Number Of Gates: 128236
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
3. At the rising edge of CCLK: If BUSY is Low, the data is
Table 11: SelectMAP Write Timing Characteristics
A flowchart for the write operation is shown in
Note that if CCLK is slower than f
asserts BUSY, In this case, the above handshake is unnec-
essary, and data can simply be entered into the FPGA every
CCLK cycle.
Abort
During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the cur-
Module 2 of 4
16
CCLK
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance instead
D
CS Setup/Hold
WRITE Setup/Hold
BUSY Propagation Delay
Maximum Frequency
Maximum Frequency with no handshake
0-7
Setup/Hold
DATA[0:7]
WRITE
CCLK
BUSY
CS
Description
No Write
5
3
CCNH
1
, the FPGA never
7
Figure 17: Write Operations
Figure
1/2
3/4
5/6
www.xilinx.com
7
Write
18.
2
4. Repeat steps 2 and 3 until all the data has been sent.
5. De-assert CS and WRITE.
rent packet command to be aborted. The device remains
BUSY until the aborted operation has completed. Following
an abort, data is assumed to be unaligned to word bound-
aries, and the FPGA requires a new synchronization word
prior to accepting any new packets.
To initiate an abort during a write operation, de-assert
WRITE. At the rising edge of CCLK, an abort is initiated, as
shown in
T
T
T
SMCSCC
occurs on the first clock after BUSY goes Low, and the
data must be held until this has happened.
SMCCW
SMDCC
No Write
T
Symbol
F
SMCKBY
Figure
F
CCNH
CC
/T
/T
/T
SMCCD
SMCCCS
SMWCC
19.
Write
Production Product Specification
4
DS022-2 (v2.8) January 16, 2006
6
5.0 / 1.7
7.0 / 1.7
7.0 / 1.7
DS022_45_071702
12.0
66
50
MHz, max
MHz, max
ns, max
ns, min
ns, min
ns, min
Units
R