XC6VCX130T-1FFG784C Xilinx Inc, XC6VCX130T-1FFG784C Datasheet - Page 26

• Manufacturer Part Number: XC6VCX130T-1FFG784C
• Description: FPGA Virtex®-6 CXT Family 128000 Cells 40nm (CMOS) Technology 1V 784-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX130T-1FFG784C

• Package: 784FCBGA
• Family Name: Virtex®-6 CXT
• Device Logic Units: 128000
• Number Of Registers: 160000
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 400
• Ram Bits: 9732096
• Number Of Logic Elements/cells: 128000
• Number Of Labs/clbs: 10000
• Total Ram Bits: 9732096
• Number Of I /o: 400
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 784-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IOB Pad Input/Output/3-State Switching Characteristics
Table 38
input delay adjustments, output delays terminating at pads
(based on standard) and 3-state delays.
T
input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
T
pad through the output buffer of an IOB pad. The delay
varies depending on the capability of the SelectIO output
buffer.
Table 38: IOB Switching Characteristics
DS153 (v1.6) February 11, 2011
Product Specification
LVDS_25
LVDSEXT_25
HT_25
BLVDS_25
RSDS_25 (point to point)
HSTL_I
HSTL_II
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL2_I
SSTL2_II
SSTL15
LVCMOS25, Slow, 2 mA
LVCMOS25, Slow, 4 mA
LVCMOS25, Slow, 6 mA
LVCMOS25, Slow, 8 mA
LVCMOS25, Slow, 12 mA
LVCMOS25, Slow, 16 mA
LVCMOS25, Slow, 24 mA
LVCMOS25, Fast, 2 mA
LVCMOS25, Fast, 4 mA
LVCMOS25, Fast, 6 mA
LVCMOS25, Fast, 8 mA
LVCMOS25, Fast, 12 mA
LVCMOS25, Fast, 16 mA
LVCMOS25, Fast, 24 mA
IOPI
IOOP
is described as the delay from IOB pad through the
is described as the delay from the O pin to the IOB
summarizes the values of standard-specific data
I/O Standard
1.09
1.09
1.09
1.09
1.09
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
0.66
0.66
0.66
0.66
0.66
0.66
0.66
0.66
0.66
0.66
0.66
0.66
0.66
0.66
-2
Speed Grade
T
IOPI
www.xilinx.com
1.09
1.09
1.09
1.09
1.09
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
0.66
0.66
0.66
0.66
0.66
0.66
0.66
0.66
0.66
0.66
0.66
0.66
0.66
0.66
-1
T
pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO
capability of the output buffer.
Table 39
described as the delay from the T pin to the IOB pad
through the output buffer of an IOB pad, when 3-state is
enabled (i.e., a high impedance state).
IOTP
is described as the delay from the T pin to the IOB
1.68
1.84
1.78
1.67
1.68
1.73
1.74
1.71
1.75
1.81
1.71
1.77
1.72
1.71
6.01
3.79
3.08
2.72
2.17
2.29
2.02
6.04
3.82
2.99
2.65
2.08
2.13
1.99
-2
Speed Grade
summarizes the value of T
T
IOOP
1.68
1.84
1.78
1.67
1.68
1.73
1.74
1.71
1.75
1.81
1.71
1.77
1.72
1.71
6.01
3.79
3.08
2.72
2.17
2.29
2.02
6.04
3.82
2.99
2.65
2.08
2.13
1.99
-1
Virtex-6 CXT Family Data Sheet
2.17
2.29
2.02
2.08
2.13
1.99
1.68
1.84
1.78
1.67
1.68
1.73
1.74
1.71
1.75
1.81
1.71
1.77
1.72
1.71
6.01
3.79
3.08
2.72
6.04
3.82
2.99
2.65
-2
Speed Grade
T
IOTP
IOTPHZ
1.68
1.84
1.78
1.67
1.68
1.73
1.74
1.71
1.75
1.81
1.71
1.77
1.72
1.71
6.01
3.79
3.08
2.72
2.17
2.29
2.02
6.04
3.82
2.99
2.65
2.08
2.13
1.99
-1
. T
IOTPHZ
Units
is
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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