XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 57
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XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
DCM Switching Characteristics
Table 76: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
4.
Outputs Clocks (Low Frequency Mode)
F
F
F
F
F
F
F
F
Input Clocks (Low Frequency Mode)
F
F
F
F
F
F
Outputs Clocks (High Frequency Mode)
F
F
F
F
F
F
F
F
Input Clocks (High Frequency Mode)
F
F
F
F
F
F
1XLFMSMIN
1XLFMSMAX
2XLFMSMIN
2XLFMSMAX
DVLFMSMIN
DVLFMSMAX
FXLFMSMIN
FXLFMSMAX
DLLLFMSMIN
DLLLFMSMAX
CLKINLFFXMSMIN
CLKINLFFXMSMAX
PSCLKLFMSMIN
PSCLKLFMSMAX
1XHFMSMIN
1XHFMSMAX
2XHFMSMIN
2XHFMSMAX
DVHFMSMIN
DVHFMSMAX
FXHFMSMIN
FXHFMSMAX
DLLHFMSMIN
DLLHFMSMAX
CLKINHFFXMSMIN
CLKINHFFXMSMAX
PSCLKHFMSMIN
PSCLKHFMSMAX
DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input
frequency.
When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55
to 55/45).
Symbol
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
CLKIN (using DLL outputs)
CLKIN (using DFS outputs only)
PSCLK
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
CLKIN (using DLL outputs)
CLKIN (using DFS outputs only)
PSCLK
www.xilinx.com
Description
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(1, 3, 4)
(1, 3, 4)
(2, 3, 4)
(2, 3, 4)
150.00
300.00
100.00
180.00
150.00
180.00
550.00
120.00
550.00
240.00
550.00
366.67
140.00
400.00
120.00
550.00
400.00
550.00
32.00
64.00
32.00
32.00
25.00
1.00
1.00
1.00
2.0
7.5
-3
Speed Grade
135.00
270.00
160.00
135.00
160.00
500.00
120.00
500.00
240.00
500.00
333.34
140.00
375.00
120.00
500.00
375.00
500.00
32.00
64.00
90.00
32.00
32.00
25.00
1.00
1.00
1.00
2.0
7.5
-2
120.00
240.00
140.00
120.00
140.00
450.00
120.00
450.00
240.00
450.00
300.00
140.00
350.00
120.00
450.00
350.00
450.00
32.00
64.00
80.00
32.00
32.00
25.00
1.00
1.00
1.00
2.0
7.5
-1
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
KHz
KHz
57