XC5VSX95T-1FF1136I Xilinx Inc, XC5VSX95T-1FF1136I Datasheet - Page 339

• Manufacturer Part Number: XC5VSX95T-1FF1136I
• Description: FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX95T-1FF1136I

• Package: 1136FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 94208
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 640
• Ram Bits: 8994816
• Number Of Logic Elements/cells: 94208
• Number Of Labs/clbs: 7360
• Total Ram Bits: 8994816
• Number Of I /o: 640
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1136-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IDELAYCTRL Timing
IDELAYCTRL Locations
Table 7-12
Table 7-12: IDELAYCTRL Switching Characteristics
As shown in
X-Ref Target - Figure 7-16
IDELAYCTRL modules exist in every I/O column in every clock region. An IDELAYCTRL
module calibrates all the IDELAY modules within its clock region. See
Clocks in Chapter 1
Figure 7-17
F
IDELAYCTRL_REF_PRECISION
T
IDELAYCTRLCO_RDY
IDELAYCTRL_REF
REFCLK
shows the IDELAYCTRL switching characteristics.
RST
RDY
illustrates the relative locations of the IDELAYCTRL modules.
Figure
Figure 7-16: Timing Relationship Between RST and RDY
Symbol
7-16, the Virtex-5 FPGA RST is an edge-triggered signal.
for the definition of a clock region.
www.xilinx.com
REFCLK frequency
REFCLK precision
Reset/Startup to Ready for IDELAYCTRL
Input/Output Delay Element (IODELAY)
T
Description
IDELAYCTRLCO_RDY
Global and Regional
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