XC5VLX50T-2FFG1136C Xilinx Inc, XC5VLX50T-2FFG1136C Datasheet - Page 296

• Manufacturer Part Number: XC5VLX50T-2FFG1136C
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG1136C

• Package: 1136FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 480
• Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6: SelectIO Resources
296
HyperTransport Protocol (HT)
Reduced Swing Differential Signaling (RSDS)
BLVDS (Bus LVDS)
The HyperTransport™ protocol (HT) also known as Lightning Data Transport (LDT), is a
low-voltage standard for high-speed interfaces. Its differential signaling based interface is
very similar to LVDS. Virtex-5 FPGA IOBs are equipped with HT buffers.
summarizes all the possible HT I/O standards and attributes supported.
Table 6-37: Allowed Attributes of the HT I/O Standard
Reduced Swing Differential Signaling (RSDS) is similar to an LVDS high-speed interface
using differential signaling. RSDS has a similar implementation to LVDS in Virtex-5
devices and is only intended for point-to-point applications.
Table 6-38: Allowed Attributes of the RSDS I/O Standard
Since LVDS is intended for point-to-point applications, BLVDS is not an EIA/TIA standard
implementation and requires careful adaptation of I/O and PCB layout design rules. The
primitive supplied in the software library for bidirectional LVDS does not use the Virtex-5
FPGA LVDS current-mode driver, instead, it uses complementary single-ended differential
drivers. Therefore, source termination is required.
transmitter termination.
X-Ref Target - Figure 6-89
IOSTANDARD
DIFF_TERM
IOSTANDARD
DIFF_TERM
BLVDS_25
BLVDS_25
Attributes
Attributes
IOB
Figure 6-89: BLVDS Transmitter Termination
www.xilinx.com
165Ω
165Ω
R
R
IBUFDS/IBUFGDS
IBUFDS/IBUFGDS
S
S
TRUE, FALSE
TRUE, FALSE
140Ω
R DIV
Z 0 = 50Ω
Z 0 = 50Ω
R DIFF = 100Ω
Primitives
Primitives
Figure 6-89
RSDS_25
HT_25
INX
IN
OBUFDS/OBUFTDS
OBUFDS/OBUFTDS
shows the BLVDS
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IOB
N/A
N/A
Table 6-38
BLVDS_25
+
-
ug190_6_83_030506
Data in