XC5VLX50T-1FF1136C Xilinx Inc, XC5VLX50T-1FF1136C Datasheet - Page 45

• Manufacturer Part Number: XC5VLX50T-1FF1136C
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FF1136C

• Package: 1136FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 480
• Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

X-Ref Target - Figure 1-22
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Clock Capable I/O
BUFR Use Models
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
BUFRs are ideal for source-synchronous applications requiring clock domain crossing or
serial-to-parallel conversion. Unlike BUFIOs, BUFRs are capable of clocking logic
resources in the FPGAs other than the IOBs.
Figure 1-22: BUFR Driving Various Logic Resources
BUFIO
BUFR
www.xilinx.com
To Region
Above
To Region
Below
Figure 1-22
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
is a BUFR design example.
Block
Block
RAM
RAM
Regional Clocking Resources
DSP
DSP
Tile
Tile
UG190_c1_22_022609
To Center
of Die
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