XC5VLX50-1FF676I Xilinx Inc, XC5VLX50-1FF676I Datasheet - Page 10

• Manufacturer Part Number: XC5VLX50-1FF676I
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FF676I

• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 440
• Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 1769472
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 13: Processor Block MIB Switching Characteristics
Table 14: Processor Block PLBM Switching Characteristics
Table 15: Processor Block PLBS0 Switching Characteristics
Table 16: Processor Block PLBS1 Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Clock-to-out and setup relative to clock
T
T
T
T
T
Clock-to-out and setup relative to clock
T
T
T
T
T
Clock-to-out and setup relative to clock
T
T
T
T
T
Clock-to-out and setup relative to clock
T
T
T
T
T
ADDRESS_CK
ADDRESS_CK
CK_CONTROL
CK_ADDRESS
CK_DATA
CONTROL_CK
DATA_CK
CK_CONTROL
CK_DATA
CONTROL_CK
DATA_CK
CK_CONTROL
CK_DATA
CONTROL_CK
DATA_CK
CK_CONTROL
CK_ADDRESS
CK_DATA
CONTROL_CK
DATA_CK
Clock Name
Clock Name
Clock Name
Clock Name
Description
Description
Description
Description
CPMMCCLK
CPMMCCLK
CPMMCCLK
CPMMCCLK
CPMMCCLK
CPMPPCS0PLBCLK
CPMPPCS0PLBCLK
CPMPPCS0PLBCLK
CPMPPCS0PLBCLK
CPMPPCS0PLBCLK
CPMPPCS1PLBCLK
CPMPPCS1PLBCLK
CPMPPCS1PLBCLK
CPMPPCS1PLBCLK
CPMPPCS1PLBCLK
CPMPPCMPLBCLK
CPMPPCMPLBCLK
CPMPPCMPLBCLK
CPMPPCMPLBCLK
CPMPPCMPLBCLK
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Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Reference Clock
Reference Clock
Reference Clock
Reference Clock
1.146
1.017
1.076
0.736
0.834
0.971
1.215
1.115
0.774
1.063
1.052
1.307
1.253
0.825
1.083
1.146
1.335
1.328
0.821
1.7
-3
-3
-3
-3
Speed Grade
Speed Grade
Speed Grade
Speed Grade
1.247
1.136
1.172
0.844
1.095
1.372
1.257
0.914
1.196
1.189
1.545
1.492
0.971
1.234
1.298
1.596
1.568
0.969
0.95
1.79
-2
-2
-2
-2
1.463
0.941
1.058
1.354
1.673
1.535
1.059
1.462
1.461
1.836
1.787
1.124
1.525
1.615
1.921
1.864
1.127
1.38
1.38
1.86
-1
-1
-1
-1
Units
Units
Units
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
10