XC4VLX15-10SFG363C Xilinx Inc, XC4VLX15-10SFG363C Datasheet - Page 29
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XC4VLX15-10SFG363C
Manufacturer Part Number
XC4VLX15-10SFG363C
Description
FPGA Virtex®-4 Family 13824 Cells 90nm (CMOS) Technology 1.2V 363-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VLX15-10SFG363C
Package
363FCBGA
Family Name
Virtex®-4
Device Logic Units
13824
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
240
Ram Bits
884736
Number Of Logic Elements/cells
13824
Number Of Labs/clbs
1536
Total Ram Bits
884736
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
363-FBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VLX15-10SFG363C
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC4VLX15-10SFG363C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Input Delay Switching Characteristics
Table 35: Input Delay Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
2.
3.
4.
IDELAYCTRL
T
F
IDELAYCTRL_REF_PRECISION
T
IDELAY
T
T
T
F
IDELAYCTRLCO_RDY
IDELAYCTRL_REF
IDELAYCTRL_RPW
IDELAYRESOLUTION
IDELAYTOTAL_ERR
IDELAYPAT_JIT
MAX
Refer to Xilinx Application Note
See the “REFCLK - Reference Clock” section (specific to IDELAYCTRL) in the
This value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps.
Units in ps peak-to-peak per tap.
Symbol
(2)
XAPP707
Reset to Ready for IDELAYCTRL
(Maximum)
REFCLK frequency
REFCLK precision
Minimum Reset pulse width
IDELAY Chain Delay Resolution
Cumulative delay at a given tap
Pattern dependent period jitter in delay
chain for clock pattern
Pattern dependent period jitter in delay
chain for random data pattern (PRBS 23)
C clock maximum frequency
for details on IDELAY timing characteristics.
Description
www.xilinx.com
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(3)
Virtex-4 FPGA User
10 ± 2
3.00
50.0
-12
200
±10
300
75
0
± 0.07[(tap −1) x 75 +34]
[(tap −1) x 75 +34]
Guide: Chapter 7, SelectIO Logic Resources.
Speed Grade
10 ± 2
3.00
50.0
-11
200
±10
250
75
0
10 ± 2
3.00
50.0
-10
200
±10
250
75
0
Note (4)
Note (4)
Units
MHz
MHz
MHz
µs
ns
ps
ps
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