XC3S700AN-5FGG484C Xilinx Inc, XC3S700AN-5FGG484C Datasheet - Page 45
![FPGA Spartan®-3AN Family 700K Gates 13248 Cells 770MHz 90nm Technology 1.2V 484-Pin FBGA](/photos/6/72/67299/pk081-484_sml.jpg)
XC3S700AN-5FGG484C
Manufacturer Part Number
XC3S700AN-5FGG484C
Description
FPGA Spartan®-3AN Family 700K Gates 13248 Cells 770MHz 90nm Technology 1.2V 484-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S700AN-5FGG484C
Package
484FBGA
Family Name
Spartan®-3AN
Device Logic Units
13248
Device System Gates
700000
Maximum Internal Frequency
770 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
372
Ram Bits
368640
Number Of Logic Elements/cells
13248
Number Of Labs/clbs
1472
Total Ram Bits
368640
Number Of I /o
372
Number Of Gates
700000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1528 - KIT STARTER SPARTAN-3 AN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S700AN-5FGG484C
Manufacturer:
XILINX
Quantity:
748
Company:
Part Number:
XC3S700AN-5FGG484C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 32: Recommended Number of Simultaneously
Switching Outputs per V
DS557 (v4.1) April 1, 2011
Product Specification
LVCMOS25
Signal Standard
(IOSTANDARD)
QuietIO
Slow
Fast
12
16
24
12
16
24
12
16
24
2
4
6
8
2
4
6
8
2
4
6
8
Banks 0,2
Bottom
CCO
Top,
16
10
12
10
36
30
24
20
12
8
7
6
–
–
8
6
3
–
–
–
–
TQG144
-GND Pair (Cont’d)
Banks 1,3
Right
Package Type
Left,
16
10
12
10
36
30
24
20
12
12
8
7
6
6
5
8
6
3
3
2
8
Banks 0,2
Bottom
Top,
76
46
33
24
18
18
14
76
60
48
36
36
–
–
6
6
3
–
–
–
–
FGG400,
FGG484,
FTG256,
FGG676
Banks 1,3
Right
Left,
76
46
33
24
18
11
18
14
76
60
48
36
36
36
www.xilinx.com
7
6
6
3
3
2
8
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 32: Recommended Number of Simultaneously
Switching Outputs per V
LVCMOS18
LVCMOS15
Signal Standard
(IOSTANDARD)
QuietIO
QuietIO
Slow
Slow
Fast
Fast
12
16
12
16
12
16
12
12
12
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
Banks 0,2
Bottom
CCO
Top,
13
13
30
24
20
16
12
10
30
21
18
8
8
7
–
–
8
7
4
–
–
–
–
7
7
–
–
7
6
–
–
–
–
TQG144
-GND Pair (Cont’d)
Banks 1,3
Right
Package Type
Left,
13
13
30
24
20
16
12
12
12
10
30
21
18
12
12
8
8
7
5
5
8
7
4
4
3
7
7
6
5
7
6
4
3
Banks 0,2
Bottom
Top,
64
34
22
18
18
64
64
48
36
55
31
18
25
10
70
40
31
–
–
9
7
4
–
–
–
–
–
–
6
–
–
–
–
FGG400,
FGG484,
FTG256,
FGG676
Banks 1,3
Right
Left,
64
34
22
18
13
10
18
64
64
48
36
36
24
55
31
18
15
10
25
10
70
40
31
31
20
9
7
4
4
3
6
4
3
45