XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 134
![FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC3S200-4TQG144I
Manufacturer Part Number
XC3S200-4TQG144I
Description
FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S200-4TQG144I
Package
144TQFP
Family Name
Spartan®-3
Device Logic Units
4320
Device System Gates
200000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
97
Ram Bits
221184
Package / Case
144-TQFP, 144-VQFP
Mounting Type
Surface Mount
Voltage - Supply
1.14 V ~ 3.465 V
Operating Temperature
-40°C ~ 100°C
Number Of I /o
97
Number Of Logic Elements/cells
*
Number Of Gates
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S200-4TQG144I
Manufacturer:
XILINX
Quantity:
1 029
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Spartan-3 FPGA Family: Pinout Descriptions
TQ144 Footprint
134
IO_L40N_7/VREF_7 18
IO_L40P_6/VREF_6 20
IO_L24N_6/VREF_6 24
51
14
IO_L01P_7/VRN_7
IO_L01N_7/VRP_7
IO_L01P_6/VRN_6 3 5
IO_L01N_6/VRP_6 3 6
7
0
Figure 44: TQ144 Package Footprint (top view). Note pin 1 indicator in top-left corner and logo orientation.
I/O: Unrestricted, general-purpose user I/O
DCI: User I/O or reference resistor input for
bank
CONFIG: Dedicated configuration pins
N.C.: No unconnected pins in this package
VCCO_LEFT
VCCO_LEFT 19
VCCO_LEFT 34
IO/VREF_7
IO_L20P_7
IO_L20N_7
IO_L21P_7
IO_L21N_7
IO_L22P_7 10
IO_L22N_7 11
IO_L23P_7 12
IO_L23N_7 13
IO_L24P_7 14
IO_L24N_7 15
IO_L40P_7 17
IO_L40N_6 21
IO_L24P_6 23
IO_L23P_6 25
IO_L23N_6 26
IO_L22P_6 27
IO_L22N_6 28
IO_L21P_6 30
IO_L21N_6 31
IO_L20P_6 32
IO_L20N_6 33
GND
GND
GND
GND
16
22
29
1
2
3
4
5
6
7
8
9
X
Bank 5
(no DCI)
Bank 0
12
16
8
4
DUAL: Configuration pin, then possible
user I/O
GCLK: User I/O or global clock buffer
input
JTAG: Dedicated JTAG port pins
GND: Ground
VCCO for Bottom Edge
www.xilinx.com
VCCO for Top Edge
Bank 1
Bank 4
12
12
4
4
VREF: User I/O or input voltage reference for
bank
VCCO: Output voltage supply for bank
VCCINT: Internal core voltage supply (+1.2V)
VCCAUX: Auxiliary voltage supply (+2.5V)
DS099-4 (v2.5) December 4, 2009
Product Specification
108 IO_L01N_2/VRP_2
107 IO_L01P_2/VRN_2
106 VCCO_RIGHT
105 IO_L20N_2
104 IO_L20P_2
103 IO_L21N_2
102 IO_L21P_2
101
100 IO_L22N_2
99 IO_L22P_2
98 IO_L23N_2/VREF_2
97 IO_L23P_2
96 IO_L24N_2
95 IO_L24P_2
94
93 IO_L40N_2
92 IO_L40P_2/VREF_2
91 VCCO_RIGHT
90 IO_L40N_3/VREF_3
8 9 IO_L40P_3
88
8 7 IO_L24N_3
8 6 IO_L24P_3
8 5 IO_L23N_3
8 4 IO_L23P_3/VREF_3
8 3 IO_L22N_3
8 2 IO_L22P_3
81
8 0 IO_L21N_3
79 IO_L21P_3
78 IO_L20N_3
77 IO_L20P_3
76 IO
75 VCCO_RIGHT
74 IO_L01N_3/VRP_3
73 IO_L01P_3/VRN_3
GND
GND
GND
GND
DS099-4_08_121103
R
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