XC2VP2-5FG256C Xilinx Inc, XC2VP2-5FG256C Datasheet - Page 53

• Manufacturer Part Number: XC2VP2-5FG256C
• Description: FPGA Virtex-II Pro™ Family 3168 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 256-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC2VP2-5FG256C

• Package: 256FBGA
• Family Name: Virtex-II Pro™
• Device Logic Units: 3168
• Number Of Registers: 2816
• Maximum Internal Frequency: 1050 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 140
• Ram Bits: 221184

Sum of Products
Each Virtex-II Pro slice has a dedicated OR gate named
ORCY, ORing together outputs from the slices carryout and
the ORCY from an adjacent slice. The ORCY gate with the
dedicated Sum of Products (SOP) chain are designed for
LUTs and MUXCYs can implement large AND gates or
other combinatorial logic functions.
DS083 (v4.7) November 5, 2007
Product Specification
4
4
4
4
R
LUT
LUT
LUT
LUT
4
4
4
4
MUXCY
MUXCY
MUXCY
MUXCY
ORCY
Slice 1
Slice 0
V
CC
4
4
4
4
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
Figure 44: Wide-Input AND Gate (16 Inputs)
Figure 44
Figure 43: Horizontal Cascade Chain
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
MUXCY
MUXCY
MUXCY
MUXCY
ORCY
Slice 2
Slice 3
V
illustrates
CC
“0”
“0”
“0”
CLB
0
0
0
0
MUXCY
MUXCY
MUXCY
MUXCY
www.xilinx.com
V
1
1
1
1
CC
4
4
4
4
Slice
Slice
implementing large, flexible SOP chains. One input of each
ORCY is connected through the fast SOP chain to the output
of the previous ORCY in the same slice row. The second input
is connected to the output of the top MUXCY in the same slice,
as shown in
LUT and MUXCY resources configured as a 16-input AND
gate.
LUT
LUT
LUT
LUT
OUT
MUXCY
MUXCY
MUXCY
MUXCY
Figure
ORCY
Slice 0
Slice 1
V
CC
43.
16
4
4
4
4
LUT
LUT
LUT
LUT
AND
DS031_41_110600
MUXCY
MUXCY
MUXCY
MUXCY
OUT
ORCY
Slice 3
Slice 2
V
CC
CLB
ds031_64_110300
SOP
Module 2 of 4
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