XC2S400E-6FGG456C Xilinx Inc, XC2S400E-6FGG456C Datasheet - Page 89

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XC2S400E-6FGG456C

Manufacturer Part Number
XC2S400E-6FGG456C
Description
FPGA Spartan®-IIE Family 400K Gates 10800 Cells 357MHz 0.15um Technology 1.8V 456-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-IIEr
Datasheet

Specifications of XC2S400E-6FGG456C

Package
456FBGA
Family Name
Spartan®-IIE
Device Logic Cells
10800
Device Logic Units
2400
Device System Gates
400000
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
329
Ram Bits
163840
Number Of Logic Elements/cells
10800
Number Of Labs/clbs
2400
Total Ram Bits
163840
Number Of I /o
329
Number Of Gates
400000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
456-BBGA
Case
BGA
Dc
05+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1327

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2S400E-6FGG456C
Manufacturer:
XILINX
Quantity:
201
Part Number:
XC2S400E-6FGG456C
Manufacturer:
XILINX
Quantity:
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Part Number:
XC2S400E-6FGG456C
Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
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0
Part Number:
XC2S400E-6FGG456C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Additional FG456 Package Pins (Continued)
FG676 Pinouts (XC2S400E, XC2S600E)
DS077-4 (2.3) June 18, 2008
Product Specification
Notes:
1.
2.
TMS
I/O
I/O, L204P
I/O, L204N
I/O, L203P
I/O, L203N
I/O, L202P_YY
I/O, L202N_YY
VCCO Bank 1 Pins
VCCO Bank 2 Pins
VCCO Bank 3 Pins
VCCO Bank 4 Pins
VCCO Bank 5 Pins
VCCO Bank 6 Pins
VCCO Bank 7 Pins
GND Pins
Not Connected Pins
VCCINT connections in XC2S400E and XC2S600E. No Connects (no internal connection) in XC2S100E, XC2S150E, XC2S200E,
and XC2S300E.
GND connections in XC2S400E and XC2S600E. No Connects (no internal connection) in XC2S100E, XC2S150E, XC2S200E, and
XC2S300E
Y4
A2
G17
G12
M14
N16
K11
P10
F15
T13
L13
N7
G6
T9
A1
Function
(2)
(2)
Pad Name
R
A2
B1
M16
AA2
H17
P16
K12
P11
F16
T14
T10
L14
H6
P7
J9
(2)
(2)
Bank
7
7
7
7
7
7
7
-
AA4
D4
G13
R17
U15
A22
K13
P12
L16
J16
J10
U7
R6
N9
J7
Pin
D3
C2
C1
D2
D1
B1
E2
E1
(1)
(2)
Output Option
LVDS Async.
XC2S600E
XC2S600E
D19
AA21
B1
G14
K16
U16
K14
N10
P13
T17
J11
M7
U8
T6
K7
All
All
(2)
-
-
-
-
(1)
www.xilinx.com
AA22
W4
N11
P14
J12
M9
B2
L7
-
-
-
-
-
-
-
(1)
Option
VREF
(2)
-
-
-
-
-
-
-
-
W19
M10
AB1
B21
N12
J13
T11
L9
-
-
-
-
-
-
-
(1)
I/O, L202P_YY
I/O, L202N_YY
Spartan-IIE FPGA Family: Pinout Tables
XC2S400E
TMS
I/O
I/O
Device-Specific Pinouts
-
-
-
AB22
Y4
M11
N13
L10
T12
J14
C3
-
-
-
-
-
-
-
(2)
AA4
C20
M12
N14
Y20
L11
K9
-
-
-
-
-
-
-
-
I/O, L202P_YY
I/O, L202N_YY
I/O, L203N_Y
I/O, L203P_Y
(2)
XC2S600E
I/O, L204N
I/O, L204P
TMS
I/O
AA22
M13
G11
K10
L12
P9
Y3
-
-
-
-
-
-
-
-
(2)
89

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