XC2S100E-6FT256C Xilinx Inc, XC2S100E-6FT256C Datasheet - Page 47
![FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 256-Pin FTBGA](/photos/6/71/67101/pk053-256_sml.jpg)
XC2S100E-6FT256C
Manufacturer Part Number
XC2S100E-6FT256C
Description
FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 256-Pin FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-IIEr
Datasheet
1.XC2S50E-6TQG144C.pdf
(108 pages)
Specifications of XC2S100E-6FT256C
Package
256FTBGA
Family Name
Spartan®-IIE
Device Logic Cells
2700
Device Logic Units
600
Device System Gates
100000
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
182
Ram Bits
40960
Number Of Logic Elements/cells
2700
Number Of Labs/clbs
600
Total Ram Bits
40960
Number Of I /o
182
Number Of Gates
100000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
Case
BGA
Dc
05+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1208
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2S100E-6FT256C
Manufacturer:
XILINX
Quantity:
3
Company:
Part Number:
XC2S100E-6FT256C
Manufacturer:
XILINX
Quantity:
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Part Number:
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Manufacturer:
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Quantity:
20 000
Part Number:
XC2S100E-6FT256C0775
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
CLB Distributed RAM Switching Characteristics
CLB Shift Register Switching Characteristics
Block RAM Switching Characteristics
DS077-3 (v2.3) June 18, 2008
Product Specification
Sequential Delays
Setup/Hold Times with Respect to Clock CLK
Clock CLK
Sequential Delays
Setup/Hold Times with Respect to Clock CLK
Clock CLK
Sequential Delays
Setup/Hold Times with Respect to Clock CLK
Clock CLK
T
T
T
T
T
T
T
T
T
Symbol
T
WS
SHCKO16
SHCKO32
AS
DS
BWCK
T
BACK
T
BDCK
BRCK
T
T
BECK
Symbol
T
T
SHCECK
T
WPH
WPL
SHDICK
Symbol
T
WC
T
/ T
/ T
/ T
T
SRPH
T
T
SRPL
REG
BPWH
BCKO
BPWL
BCCS
AH
DH
WH
/ T
/ T
/ T
/ T
/ T
R
BCKD
BCKE
BCKR
BCKW
BCKA
Clock CLK to X/Y outputs (WE active, 16 x 1 mode)
Clock CLK to X/Y outputs (WE active, 32 x 1 mode)
F/G address inputs
BX/BY data inputs (DIN)
CE input (WS)
Pulse width, High
Pulse width, Low
Clock period to meet address write cycle time
Clock CLK to X/Y outputs
BX/BY data inputs (DIN)
CE input (WS)
Pulse width, High
Pulse width, Low
Clock CLK to DOUT output
ADDR inputs
DIN inputs
EN inputs
RST input
WEN input
Pulse width, High
Pulse width, Low
CLKA -> CLKB setup time for different ports
Description
Description
Description
www.xilinx.com
Spartan-IIE FPGA Family: DC and Switching Characteristics
0.42 / 0
0.53 / 0
0.7 / 0
1.0 / 0
1.0 / 0
2.2 / 0
2.1 / 0
2.0 / 0
0.53 / 0
Min
0.7 / 0
0.6
0.8
2.1
2.1
4.2
Min
0.6
1.4
1.4
2.7
Min
1.2
2.1
2.1
-7
-7
-7
Max
Speed Grade
Max
Speed Grade
3.1
Max
1.5
1.9
Speed Grade
2.9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.1 / 0
1.1 / 0
2.5 / 0
2.3 / 0
2.2 / 0
0.5 / 0
0.6 / 0
0.8 / 0
0.6 / 0
0.8 / 0
Min
0.6
1.5
1.5
3.0
Min
Min
0.6
0.8
2.4
2.4
4.8
1.2
2.4
2.4
-6
-6
-6
Max
Max
Max
1.7
2.1
3.5
3.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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