XC95144-15PQ100I Xilinx Inc, XC95144-15PQ100I Datasheet - Page 9

• Manufacturer Part Number: XC95144-15PQ100I
• Description: CPLD XC9500 Family 3.2K Gates 144 Macro Cells 55.6MHz 0.5um (CMOS) Technology 5V 100-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: XC9500r

Specifications of XC95144-15PQ100I

• Package: 100PQFP
• Family Name: XC9500
• Device System Gates: 3200
• Number Of Macro Cells: 144
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 81
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 55.6 MHz
• Number Of Product Terms Per Macro: 90
• Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 144
• Number Of Gates: 3200
• Number Of I /o: 81
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Voltage: 5V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The internal logic of the product term allocator is shown in
Figure
DS063 (v5.5) June 25, 2007
Product Specification
8.
R
From Lower
From Upper
Macrocell
Macrocell
Figure 8: Product Term Allocator Logic
To Lower
Macrocell
Macrocell
To Upper
www.xilinx.com
Product Term
Allocator
XC9500 In-System Programmable CPLD Family
Product Term Set
Product Term Clock
Product Term Reset
Product Term OE
1
0
Global Set/Reset
Global Set/Reset
Global Clocks
D/T
DS063_08_110501
S
R
Q
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