XC95108-10TQG100C Xilinx Inc, XC95108-10TQG100C Datasheet - Page 9

• Manufacturer Part Number: XC95108-10TQG100C
• Description: CPLD XC9500 Family 2.4K Gates 108 Macro Cells 66.7MHz 0.5um (CMOS) Technology 5V 100-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: XC9500r

Specifications of XC95108-10TQG100C

• Package: 100TQFP
• Family Name: XC9500
• Device System Gates: 2400
• Number Of Macro Cells: 108
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 81
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 66.7 MHz
• Number Of Product Terms Per Macro: 90
• Memory Type: Flash
• Operating Temperature: 0 to 70 °C
• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 6
• Number Of Macrocells: 108
• Number Of Gates: 2400
• Number Of I /o: 81
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1421

The internal logic of the product term allocator is shown in
Figure
DS063 (v5.5) June 25, 2007
Product Specification
8.
R
From Lower
From Upper
Macrocell
Macrocell
Figure 8: Product Term Allocator Logic
To Lower
Macrocell
Macrocell
To Upper
www.xilinx.com
Product Term
Allocator
XC9500 In-System Programmable CPLD Family
Product Term Set
Product Term Clock
Product Term Reset
Product Term OE
1
0
Global Set/Reset
Global Set/Reset
Global Clocks
D/T
DS063_08_110501
S
R
Q
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