XC2C64A-7VQG44I Xilinx Inc, XC2C64A-7VQG44I Datasheet - Page 2
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XC2C64A-7VQG44I
Manufacturer Part Number
XC2C64A-7VQG44I
Description
CPLD CoolRunner™-II Family 1.5K Gates 64 Macro Cells 159MHz 0.18um (CMOS) Technology 1.8V 44-Pin VTQFP
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Specifications of XC2C64A-7VQG44I
Package
44VTQFP
Family Name
CoolRunnerÂ-II
Device System Gates
1500
Number Of Macro Cells
64
Maximum Propagation Delay Time
7.5 ns
Number Of User I/os
33
Number Of Logic Blocks/elements
4
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
159 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
-40 to 85 °C
Features
Programmable
Package / Case
44-TQFP, 44-VQFP
Mounting Type
Surface Mount
Voltage
1.8V
Number Of I /o
33
Memory Type
CMOS
Programmable Type
In System Programmable
Number Of Macrocells
64
Delay Time Tpd(1) Max
6.7ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
4
Number Of Gates
1500
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With
122-1536 - KIT STARTER SPARTAN-3E122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2C64A-7VQG44I
Manufacturer:
XILINX
Quantity:
5 192
Part Number:
XC2C64A-7VQG44I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
XC2C64A CoolRunner-II CPLD
RealDigital Design Technology
Xilinx® CoolRunner-II CPLDs are fabricated on a
0.18 micron process technology which is derived from lead-
ing edge FPGA product development. CoolRunner-II
CPLDs employ RealDigital, a design technique that makes
use of CMOS technology in both the fabrication and design
methodology. RealDigital design technology employs a cas-
cade of CMOS gates to implement sum of products instead
of traditional sense amplifier methodology. Due to this tech-
nology, Xilinx CoolRunner-II CPLDs achieve both high per-
formance and low power operation.
Supported I/O Standards
The CoolRunner-II 64 macrocell features both LVCMOS
and LVTTL I/O implementations. See
dard voltages. The LVTTL I/O standard is a general purpose
EIA/JEDEC standard for 3.3V applications that use an
Table 2: I
2
Notes:
1.
Typical I
16-bit up/down, Resetable binary counter (one counter per function block).
CC
CC
(mA)
vs Frequency (LVCMOS 1.8V T
0.017
0
15
10
20
5
0
0
Table 1
1.8
25
A
for I/O stan-
Figure 1: I
50
= 25°C)
3.7
50
www.xilinx.com
(1)
100
5.5
75
CC
vs Frequency
Frequency (MHz)
LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, and 1.8V applica-
tions. CoolRunner-II CPLDs are also 1.5V I/O compatible
with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C64A
1.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
IOSTANDARD
7.48
100
Attribute
150
Frequency (MHz)
LVCMOS15 requires Schmitt-trigger inputs.
11.0
150
(1)
200
Output
DS092_01_092302
V
3.3
3.3
2.5
1.8
1.5
CCIO
12.7
175
250
V
Input
DS311 (v2.3) November 19, 2008
CCIO
3.3
3.3
2.5
1.8
1.5
14.6
200
Input
V
N/A
N/A
N/A
N/A
N/A
Product Specification
REF
15.3
225
Termination
Voltage V
Board
N/A
N/A
N/A
N/A
N/A
17.77
240
T
R