XC2C64A-7CPG56I Xilinx Inc, XC2C64A-7CPG56I Datasheet - Page 6

• Manufacturer Part Number: XC2C64A-7CPG56I
• Description: CPLD CoolRunner™-II Family 1.5K Gates 64 Macro Cells 159MHz 0.18um (CMOS) Technology 1.8V 56-Pin CSBGA
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C64A-7CPG56I

• Package: 56CSBGA
• Family Name: CoolRunner™-II
• Device System Gates: 1500
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 45
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 1.8 V
• Maximum Operating Frequency: 159 MHz
• Number Of Product Terms Per Macro: 40
• Operating Temperature: -40 to 85 °C
• Features: Programmable
• Package / Case: 56-CSBGA
• Mounting Type: Surface Mount
• Voltage: 1.8V
• Number Of I /o: 45
• Memory Type: CMOS
• Programmable Type: In System Programmable
• Number Of Macrocells: 64
• Delay Time Tpd(1) Max: 6.7ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 4
• Number Of Gates: 1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XC2C64A CoolRunner-II CPLD
AC Electrical Characteristics Over Recommended Operating Conditions
6
Notes:
1.
2.
3.
4.
T
T
T
T
T
T
T
T
F
F
F
F
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
AO
APRPW
OE
PD1
PD2
SUD
SU1
SU2
HD
H
CO
TOGGLE
SYSTEM1
SYSTEM2
EXT1
EXT2
PSUD
PSU1
PSU2
PHD
PH
PCO
POE
MOE
PAO
SUEC
HEC
CW
PCW
CONFIG
Symbol
F
F
(one counter per function block).
F
Typical configuration current during
/T
TOGGLE
SYSTEM
EXT
/T
/T
(3)
(3)
OD
POD
MOD
(1/T
(4)
(1)
(2)
(2)
is the maximum frequency of a dual edge triggered T flip-flop with output enabled.
(1/T
SU1
+T
CYCLE
Propagation delay single p-term
Propagation delay OR array
Direct input register clock setup time
Setup time (single p-term)
Setup time (OR array)
Direct input register hold time
P-term hold time
Clock to output
Internal toggle rate
Maximum system frequency
Maximum system frequency
Maximum external frequency
Maximum external frequency
Direct input register p-term clock setup time
P-term clock setup time (single p-term)
P-term clock setup time (OR array)
Direct input register p-term clock hold time
P-term clock hold
P-term clock to output
Global OE to output enable/disable
P-term OE to output enable/disable
Macrocell driven OE to output enable/disable
P-term set/reset to output valid
Global set/reset to output valid
Register clock enable setup time
Register clock enable hold time
Global clock pulse width High or Low
P-term pulse width High or Low
Asynchronous preset/reset pulse width (High or Low)
Configuration time
CO
) is the maximum external frequency.
) is the internal operating frequency for a device fully populated with 16-bit up/down, Resetable binary counter
T
(1)
CONFIG
Parameter
is 2.3 mA.
(2)
(2)
(3)
(3)
www.xilinx.com
Min.
2.4
2.0
2.4
0.9
0.6
1.0
1.3
1.5
3.0
1.4
5.0
5.0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-5
Max.
50.0
500
263
238
169
159
4.6
5.0
3.9
6.0
8.0
9.0
9.0
7.3
6.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS311 (v2.3) November 19, 2008
Min.
3.3
2.5
3.3
1.7
0.9
1.7
1.4
1.7
3.7
2.2
7.5
7.5
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Product Specification
-7
Max.
10.0
11.0
11.0
50.0
300
159
141
118
108
6.7
7.5
6.0
8.4
9.7
8.3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
R