XC2C512-10FT256C Xilinx Inc, XC2C512-10FT256C Datasheet - Page 7

• Manufacturer Part Number: XC2C512-10FT256C
• Description: CPLD CoolRunner™-II Family 12K Gates 512 Macro Cells 128MHz 0.18um (CMOS) Technology 1.8V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC2C512-10FT256C

• Package: 256FTBGA
• Family Name: CoolRunner™-II
• Device System Gates: 12000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 212
• Number Of Logic Blocks/elements: 32
• Typical Operating Supply Voltage: 1.8 V
• Maximum Operating Frequency: 128 MHz
• Number Of Product Terms Per Macro: 40
• Operating Temperature: 0 to 70 °C

AC Electrical Characteristics Over Recommended Operating Conditions
DS096 (v3.2) March 8, 2007
Product Specification
Notes:
1.
2.
3.
4.
T
T
T
T
T
T
T
T
F
F
F
F
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OE
AO
APRPW
PD1
PD2
SUD
SU1
SU2
H
H
CO
TOGGLE
SYSTEM1
SYSTEM2
EXT1
EXT2
PSUD
PSU1
PSU2
PHD
PH
PCO
POE
MOE
PAO
SUEC
HEC
CW
PCW
DGSU
DGH
DGR
DGW
CDRSU
CDRH
CONFIG
Symbol
F
information).
F
one p-term per macrocell while F
F
Typical configuration current during T
/T
TOGGLE
SYSTEM1
EXT1
/T
/T
(3)
(3)
OD
POD
MOD
(4)
(1/T
(1)
(2)
(2)
R
is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet for more
SU1
(1/T
+T
Propagation delay (single p-term)
Propagation delay (OR array)
Direct input register set-up time
Setup time fast (single p-term)
Setup time (OR array)
Direct input register hold time
P-term hold time
Clock to output
Internal toggle rate
Maximum system frequency
Maximum system frequency
Maximum external frequency
Maximum external frequency
Direct input register p-term clock setup time
P-term clock setup time (single p-term)
P-term clock setup time (OR array)
Direct input register p-term clock hold time
P-term clock hold
P-term clock to output
Global OE to output enable/disable
P-term OE to output enable/disable
Macrocell driven OE to output enable/disable
P-term set/reset to output valid
Global set/reset to output valid
Register clock enable setup time
Register clock enable hold time
Global clock pulse width High or Low
P-term pulse width High or Low
Asynchronous preset/reset pulse width (High or Low)
Set-up before DataGATE latch assertion
Hold to DataGATE latch assertion
DataGATE recovery to new data
DataGATE low pulse width
CDRST setup time before falling edge GCLK2
Hold time CDRST after falling edge GCLK2
Configuration time
CYCLE
CO
) is the maximum external frequency using one p-term while F
) is the internal operating frequency for a device fully populated with 16-bit Resetable binary counter through
SYSTEM2
CONFIG
Parameter
is through the OR array.
is approximately 15mA
www.xilinx.com
EXT2
Min.
0.0
is through the OR array
3.4
2.6
3.0
2.1
1.1
1.5
0.1
1.3
2.8
2.0
7.5
7.5
4.0
3.0
1.7
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-7
Max.
XC2C512 CoolRunner-II CPLD
250
179
167
400
119
114
7.1
7.5
5.8
7.3
6.5
7.5
8.6
7.6
7.5
9.3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Min.
10.0
10.0
2.8
1.7
0.0
2.5
4.0
3.1
3.9
2.5
0.4
1.7
3.2
3.0
6.0
5.0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-10
Max.
10.0
10.2
12.5
11.6
11.5
11.0
166
128
400
116
9.2
7.9
9.3
9.2
91
85
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
7