XC2C32A-6CPG56C Xilinx Inc, XC2C32A-6CPG56C Datasheet - Page 10

• Manufacturer Part Number: XC2C32A-6CPG56C
• Description: CPLD CoolRunner™-II Family 750 Gates 32 Macro Cells 200MHz 0.18um (CMOS) Technology 1.8V 56-Pin CSBGA
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C32A-6CPG56C

• Package: 56CSBGA
• Family Name: CoolRunner™-II
• Device System Gates: 750
• Number Of Macro Cells: 32
• Maximum Propagation Delay Time: 6 ns
• Number Of User I/os: 33
• Number Of Logic Blocks/elements: 2
• Typical Operating Supply Voltage: 1.8 V
• Maximum Operating Frequency: 200 MHz
• Number Of Product Terms Per Macro: 40
• Operating Temperature: 0 to 70 °C
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.5ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 2
• Number Of Macrocells: 32
• Number Of Gates: 750
• Number Of I /o: 33
• Mounting Type: Surface Mount
• Package / Case: 56-CSBGA
• Features: Programmable
• Voltage: 1.8V
• Memory Type: CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1403

CoolRunner-II CPLD Family
Design Security
Designs can be secured during programming to prevent
either accidental overwriting or pattern theft via readback.
Four independent levels of security are provided on-chip,
10
Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option
Figure 9: Macrocell Clock Chain with DualEDGE Option Shown
Synch Reset
CLK_CT
PTC
GCK2
CTC
PTC
GCK0
GCK1
GCK2
GCK0
GCK1
GCK2
www.xilinx.com
Clock
In
Synch Rst
eliminating any electrical or visual detection of configuration
patterns. These security bits can be reset only by erasing
the entire device. See
÷10
÷12
÷14
÷16
÷2
÷4
÷6
÷8
PTC
PTC
D/T
CE
CK
D/T
CE
CK
✓
DS090_09_121201
✓
FIF
Latch
DualEDGE
FIF
Latch
DualEDGE
WP170
Q
DS090 (v3.1) September 11, 2008
Q
for more detail.
Product Specification
R