XC2C256-7TQ144C Xilinx Inc, XC2C256-7TQ144C Datasheet - Page 3
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XC2C256-7TQ144C
Manufacturer Part Number
XC2C256-7TQ144C
Description
CPLD CoolRunner™-II Family 6K Gates 256 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 144-Pin TQFP EP
Manufacturer
Xilinx Inc
Datasheet
1.XC2C32A-6QFG32C.pdf
(16 pages)
Specifications of XC2C256-7TQ144C
Package
144TQFP EP
Family Name
CoolRunnerÂ-II
Device System Gates
6000
Number Of Macro Cells
256
Maximum Propagation Delay Time
7.5 ns
Number Of User I/os
118
Number Of Logic Blocks/elements
16
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
152 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
0 to 70 °C
Case
TQFP144
Dc
05+
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2C256-7TQ144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
the same V
CoolRunner-II CPLD I/O standards.)
Table 4: CoolRunner-II CPLD Family Features
Architecture Description
CoolRunner-II CPLD is a highly uniform family of fast, low
power CPLDs. The underlying architecture is a traditional
CPLD architecture combining macrocells into Function
Blocks (FBs) interconnected with a global routing matrix,
the Xilinx Advanced Interconnect Matrix (AIM). The FBs use
a Programmable Logic Array (PLA) configuration which
allows all product terms to be routed and shared among any
of the macrocells of the FB. Design software can efficiently
synthesize and optimize logic that is subsequently fit to the
FBs and connected with the ability to utilize a very high per-
centage of device resources. Design changes are easily
and automatically managed by the software, which exploits
the 100% routability of the Programmable Logic Array within
each FB. This extremely robust building block delivers the
DS090 (v3.1) September 11, 2008
Product Specification
1.
IEEE 1532
I/O banks
Clock division
DualEDGE
Registers
DataGATE
LVTTL
LVCMOS33, 25,
18, and 15
SSTL2_1
SSTL3_1
HSTL_1
Configurable
ground
Quadruple data
security
Open drain outputs
Hot plugging
Schmitt Inputs
LVCMOS15 requires the use of Schmitt-trigger inputs.
(1)
R
CCIO
level. (See
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industry’s highest pinout retention, under very broad design
conditions. The architecture is explained in more detail with
the discussion of the underlying FBs, logic and intercon-
nect.
The design software automatically manages these device
resources so that users can express their designs using
completely generic constructs without knowledge of these
architectural details. More advanced users can take advan-
tage of these details to more thoroughly understand the
software’s choices and direct its results.
Figure 1
attach to pins and interconnect to each other within the
internal interconnect matrix. Each FB contains 16 macro-
cells. The BSC path is the JTAG Boundary Scan Control
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shows the high-level architecture whereby FBs
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CoolRunner-II CPLD Family
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